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w wm8960 stereo codec with 1w stereo class d speaker drivers and headphone drivers for portable audio applications wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews production data, october 2011, rev 4.1 copyright ? 2011 wolfson microelectronics plc control interface sdin sclk micbias dcvdd dbvdd dgnd dac -73 to 6db 1db steps, mute hp_l hp_r adcref, dacref avdd agnd vmid 50k 50k dac digital audio interface a-law and u-law support adcdat adclrc/gpio1 bclk mclk dacdat daclrc adc adc pll linput2 linput1 left mixer right mixer rinput1 adc digital filters alc volume -17.25 to +30db, 0.75db steps input pgas out3 linput3/ jd2 rinput3/ jd3 0, 13, 20, 29db, mute + - vmid + -12 -> 6db, 3db steps, mute -17.25 to +30db, 0.75db steps 0, 13, 20, 29db, mute + - vmid + -12 -> 6db, 3db steps, mute rinput2 spk_lp spk_ln spk_rp spk_rn spkgnd1 spkvdd1 mono mixer 0 to -21db, 3db steps 0 to -21db, 3db steps 0 to -21db, 3db steps 0 to -21db, 3db steps -73 to 6db 1db steps, mute 0db / -6db -73 to 6db 1db steps, mute +boost class d class d -73 to 6db 1db steps, mute +boost dac digital filters de- emphasis 3d enhance volume -12 -> 6db, 3db steps, mute -12 -> 6db, 3db steps, mute jack detect jack detect gpio1 spkgnd2 spkvdd2 w wm8960 description the wm8960 is a low power, high quality stereo codec designed for portable digital audio applications. stereo class d speaker drivers provide 1w per channel into 8 ? loads with a 5v supply. low leakage, excellent psrr and pop/click suppression mechanisms also allow direct battery connection to the speaker supply. flexible speaker boost settings allow speaker output power to be maximised while minimising other analogue supply currents. a highly flexible input configuration for up to three stereo sources is integrated, with a complete microphone interface. external component requirements are drastically reduced as no separate microphone, speaker or headphone amplifiers are required. advanced on-chip digital signal processing performs automatic level control for the microphone or line input. stereo 24-bit sigma-delta adcs and dacs are used with low power over-sampling digital interpolation and decimation filters and a flexible digital audio interface. the master clock can be input directly or generated internally by an onboard pll, supporting most commonly-used clocking schemes. the wm8960 operates at analogue supply voltages down to 2.7v, although the digital supplies can operate at voltages down to 1.71v to save power. the speaker supply can operate at up to 5.5v, providing 1w per channel into 8 ? loads. unused functions can be disabled using software control to save power. the wm8960 is supplied in a very small and thin 5x5mm qfn package, ideal for use in hand-held and portable systems. features ? dac snr 98db (?a? weighted), thd -84db at 48khz, 3.3v ? adc snr 94db (?a? weighted), thd -82db at 48khz, 3.3v ? pop and click suppression ? 3d enhancement ? stereo class d speaker driver - <0.1% thd with 1w per channel into 8 ? btl speakers - 70db psrr @217hz - 87% efficiency (1w output) - flexible internal switching clock ? on-chip headphone driver - 40mw output power into 16 ? at 3.3v - capless mode support - thd -75db at 20mw, snr 90db with 16 ? load ? microphone interface - pseudo differential for high noise immunity - integrated low noise micbias - programmable alc / limiter and noise gate ? low power consumption ? low supply voltages - analogue 2.7v to 3.6v (speaker supply up to 5.5v) - digital core and i/o: 1.71v to 3.6v ? on-chip pll provides flexible clocking scheme ? sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 ? 5x5x0.9mm qfn package applications ? games consoles ? portable media / dvd players ? mobile multimedia
wm8960 production data w pd, october 2011, rev 4.1 2 table of contents description ....................................................................................................... 1 ? features ............................................................................................................ 1 ? applications ..................................................................................................... 1 ? table of contents ......................................................................................... 2 ? pin configuration .......................................................................................... 3 ? ordering information .................................................................................. 3 ? pin description ................................................................................................ 4 ? absolute maximum ratings ........................................................................ 5 ? recommended operating conditions ..................................................... 5 ? electrical characteristics ..................................................................... 6 ? output pga gain ............................................................................................ 10 ? typical power consumption .................................................................... 11 ? signal timing requirements .................................................................... 13 ? system clock timing .............................................................................................. 13 ? audio interface timing ? master mode .......................................................... 13 ? audio interface timing ? slave mode .............................................................. 14 ? control interface timing ? 2-wire mode ....................................................... 15 ? internal power on reset circuit .......................................................... 16 ? device description ...................................................................................... 18 ? introduction ............................................................................................................ 18 ? input signal path .................................................................................................... 19 ? analogue to digital converter (adc) ............................................................ 26 ? automatic level control (alc) ......................................................................... 28 ? output signal path ................................................................................................ 31 ? analogue outputs ................................................................................................. 37 ? enabling the outputs ........................................................................................... 41 ? headphone output ................................................................................................. 41 ? class d speaker outputs .................................................................................... 42 ? volume updates ...................................................................................................... 43 ? headphone jack detect ....................................................................................... 45 ? thermal shutdown ................................................................................................ 46 ? general purpose input/output ........................................................................ 47 ? digital audio interface ........................................................................................ 48 ? audio interface control .................................................................................... 52 ? clocking and sample rates ................................................................................ 56 ? control interface................................................................................................. 63 ? power management ............................................................................................... 63 ? register map .................................................................................................. 67 ? register bits by address .................................................................................... 68 ? digital filter characteristics .............................................................. 82 ? adc filter responses ........................................................................................... 83 ? dac filter responses ........................................................................................... 83 ? de-emphasis filter responses .......................................................................... 85 ? applications information ........................................................................ 86 ? recommended external components ............................................................ 86 ? important notice ......................................................................................... 90 ? address: ..................................................................................................................... 90 ? revision history ........................................................................................... 91 ?
production data wm8960 w pd, october 2011, rev 4.1 3 pin configuration 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 top view rinput2 rinput1 linput3/jd2 linput1 linput2 rinput3/jd3 sdin spkvdd2 spk_rn spkgnd2 spk_rp spk_ln sclk dcvdd spkgnd1 micbias ordering information order code temperature range package moisture sensitivity level peak soldering temperature wm8960cgefl/v -40 ? c to +85 ? c 32-lead qfn (5x5x0.9mm) (pb-free) msl3 260c wm8960cgefl/rv -40 ? c to +85 ? c 32-lead qfn (5x5x0.9mm) (pb-free, tape and reel) msl3 260c note: reel quantity = 3500
wm8960 production data w pd, october 2011, rev 4.1 4 pin description pin no name type description 1 micbias analogue output microphone bias 2 linput3 / jd2 analogue input left channel line input / left channel positive differential mic input / jack detect input pin 3 linput2 analogue input left channel line input / left channel positive differential mic input 4 linput1 analogue input left channel single-ended mic input / left channel negative differential mic input 5 rinput1 analogue input right channel single-ended mic input / right channel negative differential mic input 6 rinput2 analogue input right channel line input / right channel positive differential mic input 7 rinput3 / jd3 analogue input right channel line input / right channel positive differential mic input / jack detect input pin 8 dcvdd supply digital core supply 9 dgnd supply digital ground (return path for both dcvdd and dbvdd) 10 dbvdd supply digital buffer (i/o) supply 11 mclk digital input master clock 12 bclk digital input / output audio interface bit clock 13 daclrc digital input / output audio interface dac left / right clock 14 dacdat digital input dac digital audio data 15 adclrc / gpio1 digital input / output audio interface adc left / right clock / gpio1 pin 16 adcdat digital output adc digital audio data 17 sclk digital input control interface clock input 18 sdin digital input/output control interface data input / 2-wire acknowledge output 19 spk_rn analogue output right speaker negative output 20 spkgnd2 supply ground for speaker drivers 2 21 spkvdd2 supply supply for speaker drivers 2 22 spk_rp analogue output right speaker positive output 23 spk_ln analogue output left speaker negative output 24 spkgnd1 supply ground for speaker drivers 1 25 spk_lp analogue output left speaker positive output 26 spkvdd1 supply supply for speaker drivers 1 27 vmid analogue output midrail voltage decoupling capacitor 28 agnd supply analogue ground (return path for avdd) 29 hp_r analogue output right output (line or headphone) 30 out3 analogue output mono, left, right or buffered midrail output for capless mode 31 hp_l analogue output left output (line or headphone) 32 avdd supply analogue supply 33 gnd_paddle die paddle (note 1) note: 1. it is recommended that the qfn ground paddle should be connected to analogue ground on the application pcb.
production data wm8960 w pd, october 2011, rev 4.1 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional oper ating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j- std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 ? c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max supply voltages (excluding spkvdd1 and spkvdd2) -0.3v +4.5v spkvdd1, spkvdd2 -0.3v +7v voltage range digital inputs dgnd -0.3v dbvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v operating temperature range, t a -40 ? c +85 ? c storage temperature after soldering -65 ? c +150 ? c notes: 1. analogue, digital and speaker grounds must always be within 0.3v of each other. 2. all digital and analogue supplies are completely i ndependent from each other (i.e. not internally connected). 3. dcvdd must be less than or equal to avdd and dbvdd. 4. avdd must be less than or equal to spkvdd1 and spkvdd2. 5. spkvdd1 and spkvdd2 must be high enough to support the peak output voltage when using dcgain and acgain functions, to avoid output waveform clipping. peak output voltage is avdd*(dcgain+acgain)/2. recommended operating conditions parameter symbol min typ max unit digital supply range (core) dcvdd 1.71 3.6 v digital supply range (buffer) dbvdd 1.71 3.6 v analogue supplies range avdd 2.7 3.6 v speaker supply range spkvdd1, spkvdd2 2.7 5.5 v ground dgnd, agnd, spkgnd1, spkgnd2 0 v
wm8960 production data w pd, october 2011, rev 4.1 6 electrical characteristics test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = spkvdd1 = spkvdd2 = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit analogue inputs (linput1, rinput1, linput2, linput3, rinput2, rinput3) full-scale input signal level ? note this changes in proportion to avdd v infs l/rinput1,2,3 single-ended 1.0 0 vrms dbv l/rinput1,2,3 differential mic 0.5 -6 vrms dbv mic pga equivalent input noise 0 to 20khz, +30db gain 150 uv input resistance (note that input boost and bypass path resistances will be seen in parallel with pga input resistance when these paths are enabled) l/r input1 +30db pga gain differential or single- ended mic configuration 3 k ? l/r input1 0db pga gain differential or single- ended mic configuration 49 k ? l/r input1 -17.25db pga gain differential or single- ended mic configuration 87 k ? l/r input2, l/r input3 (constant for all gains) differential mic configuration 85 k ? l/r input2, l/r input3 max boost gain l/rinput2/3 to boost 7.5 k ? l/r input2, l/r input3 0db boost gain l/rinput2/3 to boost 13 k ? l/r input2, l/r input3 min boost gain l/rinput2/3 to boost 37 k ? l/r input3 max bypass gain l/rinput3 to bypass 17 k ? l/r input3 min bypass gain l/rinput3 to bypass 70 k ? input capacitance 10 pf mic programmable gain amplifier (pga) programmable gain min -17.25 db programmable gain max 30 db programmable gain step size guaranteed monotonic 0.75 db mute attenuation lmic2b = 0 and rmic2b = 0 85 db selectable input gain boost gain boost steps input from pga 0, 13, 20, 29, mute db input from l/rinput2 or l/rinput3 -12, -9, -6, -3, 0, 3, 6, mute db analogue inputs (linput1/2 differential, rinput1/2 differential) to adc out via mic pga signal to noise ratio (a-weighted) snr avdd = 3.3v 94 db avdd = 2.7v 93 total harmonic distortion plus noise thd+n -3dbfs input, avdd = 3.3v -86 0.005 db % -3dbfs input, avdd = 2.7v -80 0.01
production data wm8960 w pd, october 2011, rev 4.1 7 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = spkvdd1 = spkvdd2 = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit total harmonic distortion thd -3dbfs input, avdd = 3.3v -89 0.004 db % -3dbfs input, avdd = 2.7v -81 0.009 analogue inputs (linput2, rinput2) to adc out signal to noise ratio (a-weighted) snr avdd = 3.3v 84 94 db avdd = 2.7v 93 total harmonic distortion plus noise thd+n -3dbfs input, avdd = 3.3v -86 0.005 -80 db % -3dbfs input, avdd = 2.7v -80 0.01 total harmonic distortion thd -3dbfs input, avdd = 3.3v -89 0.004 -80 db % -3dbfs input, avdd = 2.7v -81 0.009 analogue inputs (linput3, rinput3) to adc out signal to noise ratio (a-weighted) snr avdd = 3.3v 94 db avdd = 2.7v 93 total harmonic distortion plus noise thd+n -3dbfs input, avdd = 3.3v -86 0.005 db % -3dbfs input, avdd = 2.7v -80 0.01 total harmonic distortion thd -3dbfs input, avdd = 3.3v -89 0.004 db % -3dbfs input, avdd = 2.7v -81 0.009 analogue inputs (linput1, rinput1, linput2, rinput2, linput3, rinput3) to adc out adc channel separation 1khz full scale signal into adc via l/rinput1, mic amp (single-ended) and boost 95 db 1khz full scale signal into adc via l/rinput1/2, mic amp (pseudo- differential) and boost 85 db 1khz full scale signal into adc via l/rinput2 and boost 85 db 1khz full scale signal into adc via l/rinput3 and boost 92 db line input / mic separation (quiescent input to adc via boost; output on adc; 1khz on l/rinput3 to hp out via bypass path) single-ended mic input on l/rinput1 98 db differential mic input using l/rinput2 90 db boost / bypass separation (quiescent l/rinput3 to hp outputs via bypass) 1khz on linput2 to adc via boost only 96 db 1khz on linput1 to adc via single-ended mic pga & boost 116 db channel matching 1khz signal 0.2 db
wm8960 production data w pd, october 2011, rev 4.1 8 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = spkvdd1 = spkvdd2 = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit headphone outputs (hp_l, hp_r) 0db full scale output voltage avdd/3.3 vrms mute attenuation 1khz, full scale signal 86 db channel separation l/rinput3 to headphone outputs via bypass 110 db dac to line-out (hp_l or hp_r with 10k ? / 50pf load) signal to noise ratio (a-weighted) snr avdd=3.3v 90 99 db avdd=2.7v 98 total harmonic distortion plus noise thd+n avdd=3.3v -85 -80 db avdd=2.7v -90 total harmonic distortion thd avdd=3.3v -87 -80 db avdd=2.7v -92 channel separation 1khz full scale signal 110 db dac to line-out (out3 with 10k ? / 50pf load) signal to noise ratio (a-weighted) snr avdd=3.3v 99 db avdd=2.7v 98 total harmonic distortion plus noise thd+n avdd=3.3v -85 db avdd=2.7v -90 total harmonic distortion thd avdd=3.3v -87 db avdd=2.7v -92 channel separation 1khz full scale signal 110 db headphone output (hp_l, hp_r, using capacitors unless otherwise specified) output power per channel p o output power is very closely correlated with thd; see below. total harmonic distortion plus noise thd+n avdd=2.7v, r l =32 ? p o =5mw -78 0.013 db % avdd=2.7v, r l =16 ? p o =5mw -75 0.018 avdd=3.3v, r l =32 ? , p o =20mw -72 0.025 avdd=3.3v, r l =16 ? , p o =20mw -70 0.032 signal to noise ratio (a-weighted) snr avdd = 3.3v 92 99 db avdd = 2.7v 98 speaker outputs (dac to spk_lp, spk_ln, spk_rp, spk_rn with 8 ? bridge tied load) output power p o output power is very closely correlated with thd; see below total harmonic distortion plus noise (dac to speaker outputs) thd+n p o =200mw, r l = 8 ? , spkvdd1=spkvdd2 =3.3v; avdd=3.3v -78 0.013 db % p o =320mw, r l = 8 ? , spkvdd1=spkvdd2 =3.3v; avdd=3.3v -72 0.025 db % p o =500mw, r l = 8 ? , spkvdd1=spkvdd2 =5v; avdd=3.3v -75 0.018 db % p o =1w, r l = 8 ? , spkvdd1=spkvdd2 =5v; avdd=3.3v -70 0.032 db %
production data wm8960 w pd, october 2011, rev 4.1 9 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = spkvdd1 = spkvdd2 = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit total harmonic distortion plus noise (linput3 and rinput3 to speaker outputs) thd+n p o =200mw, r l = 8 ? , spkvdd1=spkvdd2 =3.3v; avdd=3.3v -78 0.013 db % p o =320mw, r l = 8 ? , spkvdd1=spkvdd2 =3.3v; avdd=3.3v -72 0.025 db % p o =500mw, r l = 8 ? , spkvdd1=spkvdd2 =5v; avdd=3.3v -75 0.018 db % p o =1w, r l = 8 ? , spkvdd1=spkvdd2 =5v; avdd=3.3v -70 0.032 db % signal to noise ratio (a-weighted) (dac to speaker outputs) snr spkvdd1=spkvdd2 =3.3v; avdd=3.3v; r l = 8 ? , ref=2.0vrms 90 db spkvdd1=spkvdd2 =5v; avdd=3.3v; r l = 8 ? , ref=2.8vrms 92 db signal to noise ratio (a-weighted) (linnput3 and rinput3 to speaker outputs) snr spkvdd1=spkvdd2 =3.3v; avdd=3.3v; r l = 8 ? , ref=2.0vrms 90 db spkvdd1=spkvdd2 =5v; avdd=3.3v; r l = 8 ? , ref=2.8vrms 92 db speaker supply leakage current i spkvdd spkvdd1=spkvdd2 =5v; all other supplies disconnected 1 ua spkvdd1=spkvdd2 =5v; all other supplies 0v 1 ua power supply rejection ratio (100mv ripple on spkvdd1/spkvdd2 @217hz) psrr dac to speaker playback 80 db l/rinput3 to speaker playback 80 db analogue reference levels midrail reference voltage vmid ?3% avdd/2 +3% v microphone bias bias voltage v micbias 3ma load current mbsel=1 ?5% 0.9 ? avdd + 5% v 3ma load current mbsel=0 ?5% 0.65 ? avdd + 5% v bias current source i micbias 3 ma output noise voltage vn 1k to 20khz 15 nv/ ? hz digital input / output input high level v ih 0.7 ? dbvdd v input low level v il 0.3 ? dbvdd v output high level v oh i ol =1ma 0.9 ? dbvdd v output low level v ol i oh =-1ma 0.1 ? dbvdd v input capacitance 10 pf input leakage -0.9 0.9 ua
wm8960 production data w pd, october 2011, rev 4.1 10 output pga gain output pga gains (target gain, not measured) -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 20 40 60 80 100 120 140 volume register setting gain (db) figure 1 output pga gains (lout1vol, rout1vol, spklvol, spkrvol)
production data wm8960 w pd, october 2011, rev 4.1 11 typical power consumption dcvdd (v) dbvdd (v) spkvdd (v) avdd (v) dcvdd (ma) dbvdd (ma) spkvdd (ma) avdd (ma) total power (mw) 1.71 1.71 2.7 2.7 0.00 0.00 0.00 0.03 0.08 1.8 1.8 3 3 0.00 0.00 0.00 0.03 0.10 1.8 3.3 3.3 3.3 0.00 0.00 0.00 0.03 0.11 3.6 3.6 5.5 3.6 0.00 0.00 0.00 0.03 0.13 1.71 1.71 2.7 2.7 0.00 0.00 0.00 0.01 0.02 1.8 1.8 3 3 0.00 0.00 0.00 0.01 0.03 1.8 3.3 3.3 3.3 0.00 0.00 0.00 0.01 0.03 3.6 3.6 5.5 3.6 0.00 0.00 0.00 0.01 0.04 1.71 1.71 2.7 2.7 0.00 0.00 0.00 0.03 0.09 1.8 1.8 3 3 0.00 0.00 0.00 0.04 0.11 1.8 3.3 3.3 3.3 0.00 0.00 0.00 0.04 0.12 3.6 3.6 5.5 3.6 0.00 0.00 0.00 0.04 0.13 off, sleep mode sleep - thermal sensors enabled, vmid enabled using 250k vmid resistors off - thermal sensor disabled, no clocks off - default state at power up dcvdd (v) dbvdd (v) spkvdd (v) avdd (v) dcvdd (ma) dbvdd (ma) spkvdd (ma) avdd (ma) total power (mw) 1.71 1.71 2.7 2.7 3.15 0.00 1.45 4.89 22.5 1.8 1.8 3 3 3.34 0.00 1.63 5.53 27.5 1.8 3.3 3.3 3.3 3.33 0.01 1.81 6.18 32.4 3.6 3.6 5.5 3.6 7.53 0.00 3.23 6.85 69.5 1.71 1.71 2.7 2.7 3.27 0.00 267 4.93 738.5 1.8 1.8 3 3 3.47 0.00 293 5.58 902.4 1.8 3.3 3.3 3.3 3.47 0.01 321 6.23 1085.6 3.6 3.6 5.5 3.6 8.76 0.01 511 6.54 2868.2 1.71 1.71 2.7 2.7 2.99 0.47 1.47 5.82 25.6 1.8 1.8 3 3 3.16 0.49 1.65 6.57 31.2 1.8 3.3 3.3 3.3 3.16 0.92 1.84 7.34 39.0 3.6 3.6 5.5 3.6 7.95 1.00 3.29 8.12 79.6 1.71 1.71 2.7 2.7 3.15 0.00 0.00 3.75 15.5 1.8 1.8 3 3 3.33 0.00 0.00 4.24 18.7 1.8 3.3 3.3 3.3 3.33 0.01 0.00 4.74 21.7 3.6 3.6 5.5 3.6 8.25 0.00 0.00 5.25 48.6 1.71 1.71 2.7 2.7 3.26 0.00 0.00 38.68 110.0 1.8 1.8 3 3 3.46 0.00 0.00 43.53 136.8 1.8 3.3 3.3 3.3 3.46 0.01 0.00 48.32 165.7 3.6 3.6 5.5 3.6 8.52 0.00 0.00 53.06 221.7 1.71 1.71 2.7 2.7 3.26 0.00 0.00 17.44 52.7 1.8 1.8 3 3 3.44 0.00 0.00 17.91 59.9 1.8 3.3 3.3 3.3 3.45 0.01 0.00 18.37 66.9 3.6 3.6 5.5 3.6 8.51 0.00 0.00 18.84 98.5 1.71 1.71 2.7 2.7 3.25 0.00 0.00 5.47 20.3 1.8 1.8 3 3 3.45 0.00 0.00 5.92 24.0 1.8 3.3 3.3 3.3 3.45 0.01 0.00 6.37 27.2 3.6 3.6 5.5 3.6 8.49 0.00 0.00 6.83 55.2 1.71 1.71 2.7 2.7 2.97 0.47 0.00 4.69 18.5 1.8 1.8 3 3 3.14 0.49 0.00 5.29 22.4 1.8 3.3 3.3 3.3 3.14 0.92 0.00 5.91 28.2 3.6 3.6 5.5 3.6 7.91 1.01 0.00 6.55 55.7 1.71 1.71 2.7 2.7 3.26 0.00 0.00 3.81 15.9 1.8 1.8 3 3 3.46 0.00 0.00 4.30 19.1 1.8 3.3 3.3 3.3 3.45 0.01 0.00 4.80 22.1 3.6 3.6 5.5 3.6 8.51 0.00 0.00 5.31 49.8 1.71 1.71 2.7 2.7 0.28 0.00 1.47 3.07 12.7 1.8 1.8 3 3 0.30 0.00 1.64 3.48 15.9 1.8 3.3 3.3 3.3 0.30 0.01 1.82 3.91 19.5 3.6 3.6 5.5 3.6 0.76 0.00 3.27 4.35 36.4 1.71 1.71 2.7 2.7 0.00 0.00 0.00 1.84 5.0 1.8 1.8 3 3 0.00 0.00 0.00 2.09 6.3 1.8 3.3 3.3 3.3 0.00 0.00 0.00 2.36 7.8 3.6 3.6 5.5 3.6 0.00 0.00 0.00 2.62 9.5 bypass mode - stereo playback bypassing adc and dac to 16ohm hp (no signal) bypass mode - stereo playback bypassing adc and dac to class d 8ohm speaker (no signal) playback mode - playback to 10kohm hp, slave mode (0db fs 1khz signal) playback mode - playback to 16ohm hp, master mode, pll enabled (no signal) playback mode - playback to 16ohm hp, slave mode. (0.1mw/channel output) playback mode - playback to 16ohm hp, slave mode (5mw/channel output) playback mode - playback to 8ohm speakers, slave mode (no signal) playback mode playback mode - playback to 8ohm speakers, slave mode (0db fs 1khz signal) playback mode - playback to 8ohm speakers, master mode, pll enabled (no signal) playback mode - playback to 16ohm hp, slave mode. no signal playback mode - playback to 16ohm hp, slave mode (0db fs 1khz signal)
wm8960 production data w pd, october 2011, rev 4.1 12 dcvdd (v) dbvdd (v) spkvdd (v) avdd (v) dcvdd (ma) dbvdd (ma) spkvdd (ma) avdd (ma) total power (mw) 1.71 1.71 2.7 2.7 1.10 0.01 0.00 5.84 17.7 1.8 1.8 3 3 1.17 0.01 0.00 6.24 20.8 1.8 3.3 3.3 3.3 1.17 0.01 0.00 6.64 24.1 3.6 3.6 5.5 3.6 2.92 0.01 0.00 7.05 35.9 1.71 1.71 2.7 2.7 2.99 0.01 0.00 5.99 21.3 1.8 1.8 3 3 3.19 0.01 0.00 6.41 25.0 1.8 3.3 3.3 3.3 3.19 0.03 0.00 6.83 28.4 3.6 3.6 5.5 3.6 7.94 0.02 0.00 7.26 54.8 1.71 1.71 2.7 2.7 3.27 0.02 0.00 6.01 21.9 1.8 1.8 3 3 3.47 0.02 0.00 6.44 25.6 1.8 3.3 3.3 3.3 3.47 0.03 0.00 6.86 29.0 3.6 3.6 5.5 3.6 8.63 0.03 0.00 7.29 57.4 1.71 1.71 2.7 2.7 3.01 0.01 0.00 5.99 21.4 1.8 1.8 3 3 3.20 0.02 0.00 6.41 25.0 1.8 3.3 3.3 3.3 3.20 0.03 0.00 6.84 28.4 3.6 3.6 5.5 3.6 7.97 0.03 0.00 7.27 54.9 record mode record mode - stereo i/p into adc sampling at 16khz (no signal) record mode - stereo i/p into adc sampling at 44.1khz (no signal) record mode - stereo i/p into adc sampling at 48khz (no signal) record mode - stereo i/p into adc sampling at 44.1khz with alc enabled (no signal) note: 1. power in the load is included.
production data wm8960 w pd, october 2011, rev 4.1 13 signal timing requirements system clock timing figure 2 system clock timing requirements test conditions dcvdd=1.8v, dbvdd=avdd=spkv dd1=spkvdd2=3.3v, dgnd=ag nd=spkgnd1=spkgnd2=0v, t a = +25 o c parameter symbol conditions min typ max unit system clock timing information mclk cycle time t mclky 33.33 ns mclk duty cycle t mclkds 60:40 40:60 audio interface timing ? master mode figure 2 digital audio data timing ? master mode (see control interface) mclk t mclk y
wm8960 production data w pd, october 2011, rev 4.1 14 test conditions dcvdd=1.8v, dbvdd=avdd =spkvdd1=spkvdd2=3.3v, dgnd=a gnd=spkgnd1=spkgnd2=0v, t a =+25 o c, slave mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information adclrc/daclrc propagation delay from bclk falling edge t dl 10 ns adcdat propagation delay from bclk falling edge t dda 10 ns dacdat setup time to bclk rising edge t dst 10 ns dacdat hold time from bclk rising edge t dht 10 ns audio interface timing ? slave mode figure 3 digital audio data timing ? slave mode test conditions dcvdd=1.8v, dbvdd=avdd=spkvdd 1=spkvdd2=3.3v, dgnd=agnd= spkgnd1=spkgnd2=0v, t a =+25 o c, slave mode, fs=48khz, mclk= 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns adclrc/daclrc set-up time to bclk rising edge t lrsu 10 ns adclrc/daclrc hold time from bclk rising edge t lrh 10 ns dacdat hold time from bclk rising edge t dh 10 ns adcdat propagation delay from bclk falling edge t dd 10 ns dacdat set-up time to bclk rising edge t ds 10 ns note: bclk period should always be greater than or equal to mclk period.
production data wm8960 w pd, october 2011, rev 4.1 15 control interface timing ? 2-wire mode sdin sclk t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 figure 4 control interface timing ? 2-wire serial control mode test conditions dcvdd=1.8v, dbvdd=avdd=spkv dd1=spkvdd2=3.3v, dgnd=ag nd=spkgnd1=spkgnd2=0v, t a =+25 o c, slave mode, fs=48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk frequency 526 khz sclk low pulse-width t 1 1.3 us sclk high pulse-width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns
wm8960 production data w pd, october 2011, rev 4.1 16 internal power on reset circuit figure 5 internal power on reset circuit schematic the wm8960 includes an internal power-on-reset circ uit, as shown in figure 5, which is used to reset the digital logic into a default state after power up. the por circuit is powered from avdd and monitors dcvdd. it asserts porb low if av dd or dcvdd is below a minimum threshold. figure 6 typical power up sequence where avdd is powered before dcvdd figure 6 shows a typical power-up sequence wher e avdd comes up first. when avdd goes above the minimum threshold, v pora , there is enough voltage for the circuit to guarantee porb is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. now avdd is at full supply level. next dcvdd rises to v pord_on and porb is released high and all registers are in their default state and writes to the control interface may take place. on power down, where avdd falls first, porb is asserted low whenever avdd drops below the minimum threshold v pora_off .
production data wm8960 w pd, october 2011, rev 4.1 17 figure 7 typical power up sequence where dcvdd is powered before avdd figure 7 shows a typical power-up sequence where dcvdd comes up first. first it is assumed that dcvdd is already up to specified operating voltage. when avdd goes above the minimum threshold, v pora , there is enough voltage for the circuit to guarantee porb is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. when avdd rises to v pora_on , porb is released high and all registers ar e in their default state and writes to the control interface may take place. on power down, where dcvdd falls first, porb is asserted low whenever dcvdd drops below the minimum threshold v pord_off . symbol min typ max unit v pora 0.4 0.6 0.8 v v pora_on 0.9 1.2 1.6 v v pora_off 0.4 0.6 0.8 v v pord_on 0.5 0.7 0.9 v v pord_off 0.4 0.6 0.8 v table 1 typical por operation (typical values, not tested) notes: 1. if avdd and dcvdd suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below v pora_off or v pord_off ) then the chip will not reset and will resume normal operation when the voltage is back to the recommended level again. 2. the chip will enter reset at power down when avdd or dcvdd falls below v pora_off or v pord_off . this may be important if the supply is turned on and off frequently by a power management system. 3. the minimum t por period is maintained even if dcvdd and avdd have zero rise time. this specification is guaranteed by design rather than test.
wm8960 production data w pd, october 2011, rev 4.1 18 device description introduction the wm8960 is a low power audio codec offering a combination of high quality audio, advanced features, low power and small size. these characteristics make it ideal for portable digital audio applications with stereo speaker and headphone outputs such as games consoles, portable media players and multimedia phones. stereo class d speaker drivers can provide >1w per channel into 8 ? loads. btl configuration provides high power output and excellent psrr. low leakage and pop/click suppression mechanisms allow direct battery connection, reducing component count and power consumption in portable battery-powered applications. highly flexible speaker boost settings provide fully internal level-shifting of analogue output signals, allowing speaker output power to be maximised while minimising other analogue supply currents, and requiring no additional components. a flexible input configuration includes support for two stereo microphone interfaces (single-ended or pseudo-differential) and additional stereo line inputs. up to three stereo analogue input sources are available, removing the need for external analogue switc hes in many applications. boost amplifiers are available for additional gain on the microphone inputs and a programmable gain amplifier with a mixed signal automatic level control (alc) keeps the recording volume constant. the stereo adc and dac are of hi-fi quality using a 24-bit, low-order oversampling architecture to deliver optimum performance. a flexible clocking arrangement supports mixed adc and dac sample rates. the dac output signal can be mixed with analogue input signals from the line inputs or bypass paths. this mix is available on speaker and headphone/line outputs. the wm8960 has a configurable digital audio interface where adc data can be read and digital audio playback data fed to the dac. it supports a number of audio data formats including i 2 s, dsp mode (a burst mode in which frame sync plus two data packed words are transmitted), msb-first, left justified and msb-first, right justified, and can operate in master or slave modes. in pcm mode a-law and ? - law companding is supported. the sysclk (system clock) provides clocking for the adcs, dacs, dsp core, class d outputs and the digital audio interface. sysclk can be derived directly from the mclk pin or via an integrated pll, providing flexibility to support a wide range of clocking schemes. all mclk frequencies typically used in portable systems are supported for sample rates between 8khz and 48khz. a flexible switching clock for the class d speaker driver s (synchronous with the audio dsp clocks for best performance) is also derived from sysclk. to allow full software control over all its features, the wm8960 uses a 2 wire control interface. it is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and dsps. unused circuitry can be disabled via software to save power, while low leakage currents extend standby and off time in portable battery-powered applications.
production data wm8960 w pd, october 2011, rev 4.1 19 input signal path the wm8960 has three flexible stereo analogue input channels which can be configured as line inputs, differential microphone inputs or single-ended microphone inputs. line inputs and microphone pga outputs can be routed to the hi-fi adcs or directly to the output mixers via a bypass path. microphone inputs differential microphones can be connected between linput1 and linput2 or linput3, and between rinput1 and rinput2 or rinput3. alternatively single-ended microphones can be connected to linput1 or rinput1. in single-ended microphone input configuration the microphone signal should be input to linput1 or rinput1 and the internal non-inverting input of the input pga should be switched to vmid. in differential mode the larger signal should be i nput to linput2 or linput3 on the left channel, or rinput2 or rinput3 on the right channel. the smaller (e.g. noisy ground connection) should be input to linput1 or rinput1. the gain of the microphone pgas can be controlled directly via software, or using the alc / limiter. the inputs linput2, rinput2, linput3 and rinput3 should not be connected to the boost mixer or bypass path while operating as the non-inverting input in differential microphone configuration.
wm8960 production data w pd, october 2011, rev 4.1 20 figure 8 microphone input pga circuit the input pgas and boost mixers are enabled by the ainl and ainr register bits. the microphone pgas can be also be disabled independently of the boost mixer to save power, using lmic and rmic register bits. register address bit label default description r25 (19h) power management (1) 5 ainl 0 left channel input pga and boost stage enable 0 = pga disabled, boost disabled 1 = pga enabled (if lmic = 1), boost enabled 4 ainr 0 right channel input pga and boost stage enable 0 = pga disabled, boost disabled 1 = pga enabled (if lmic = 1), boost enabled r47 (2fh) power management (3) 5 lmic 0 left channel input pga enable 0 = pga disabled 1 = pga enabled (if ainl = 1) 4 rmic 0 right channel input pga enable 0 = pga disabled 1 = pga enabled (if ainr = 1) table 2 input pga and boost enable register settings the input pgas can be configured as diff erential inputs, using linput1/linput2 or linput1/linput3, and rinput1/rinput2 or rinput1/rinput3. the input impedance to these non-inverting inputs is constant in this configuration. differential configuration is controlled by lmp2, lmp3, rmp2 and rmp3 as shown in table 3. when single-ended configuration is selected, the non-inverting input of the pga is connected to vmid.
production data wm8960 w pd, october 2011, rev 4.1 21 register address bit label default description r32 (20h) adcl input signal path 3 lmic2b 0 connect left input pga to left input boost mixer 0 = not connected 1 = connected 6 lmp2 0 connect linput2 to non-inverting input of left input pga 0 = linput2 not connected to pga 1 = linput2 connected to pga (constant input impedance) 7 lmp3 0 connect linput3 to non-inverting input of left input pga 0 = linput3 not connected to pga 1 = linput3 connected to pga (constant input impedance) 8 lmn1 1 connect linput1 to inverting input of left input pga 0 = linput1 not connected to pga 1 = linput1 connected to pga r33 (21h) adcr input signal path 3 rmic2b 0 connect right input pga to right input boost mixer 0 = not connected 1 = connected 6 rmp2 0 connect rinput2 to non-inverting input of right input pga 0 = rinput2 not connected to pga 1 = rinput2 connected to pga (constant input impedance) 7 rmp3 0 connect rinput3 to non-inverting input of right input pga 0 = rinput3 not connected to pga 1 = rinput3 connected to pga (constant input impedance) 8 rmn1 1 connect rinput1 to inverting input of right input pga 0 = rinput1 not connected to pga 1 = rinput1 connected to pga table 3 input pga control input pga volume controls the input pgas have a gain range from -17.25db to +30db in 0.75db steps. the gains from the inverting inputs (linput1 and rinput1) to the pga outputs and from the non-inverting inputs (linput2/rinput2 and linput3/rinput3) to the pga output are always common in differential configuration and controlled by the register bits linvol[5:0] and rinvol[5:0]. when the automatic level control (alc) is enabled the input pga gains are controlled automatically and the linvol and rinvol bits should not be used. the left and right input pgas can be independently m uted using the linmute and rinmute register bits. to allow simultaneous volume updates of left and right channels, pga gains are not altered until a 1 is written to the ipvu bit. to prevent "zipper noise", a zero-cross function is provided, so that when enabled, volume updates will not take place until a zero-crossing is detected. in the event of a long period without zero- crossings, a timeout function is available. when this function is enabled (using the toen register bit), the volume will update automatically after a timeout. the timeout period is set by toclksel. note that sysclk must be running to use this function.
wm8960 production data w pd, october 2011, rev 4.1 22 register address bit label default description r0 (00h) left channel pga 8 ipvu n/a input pga volume update writing a 1 to this bit will cause left and right input pga volumes to be updated (linvol and rinvol) 7 linmute 1 left input pga analogue mute 1 = enable mute 0 = disable mute note: ipvu must be set to un-mute. 6 lizc 0 left input pga zero cross detector 1 = change gain on zero cross only 0 = change gain immediately 5:0 linvol [5:0] 010111 ( 0db ) left input pga volume control 111111 = +30db 111110 = +29.25db . . 0.75db steps down to 000000 = -17.25db r1 (01h) right channel pga 8 ipvu n/a input pga volume update writing a 1 to this bit will cause left and right input pga volumes to be updated (linvol and rinvol) 7 rinmute 1 right input pga analogue mute 1 = enable mute 0 = disable mute note: ipvu must be set to un-mute. 6 rizc 0 right input pga zero cross detector 1 = change gain on zero cross only 0 = change gain immediately 5:0 rinvol [5:0] 010111 ( 0db ) right input pga volume control 111111 = +30db 111110 = +29.25db . . 0.75db steps down to 000000 = -17.25db r23 (17h) additional control (1) 0 toen 0 timeout enable (also enables jack detect debounce clock) 0 = timeout disabled 1 = timeout enabled 1 toclksel 0 slow clock selection (used for volume update timeouts and for jack detect debounce) 0 = sysclk / 2 21 (slower response) 1 = sysclk / 2 19 (faster response) table 4 input pga volume control see "volume updates" for more information on volume update bits, zero cross and timeout operation. line inputs two pairs of stereo line inputs (linput2 / rinp ut2 and linput3 / rinput3) are available as analogue inputs into the adc path. linput3 and rinp ut3 can also be input directly to the output mixers via the bypass paths. see "output signal path" for more information on the bypass paths.
production data wm8960 w pd, october 2011, rev 4.1 23 input boost the input path to the adcs is via a boost stage, which can mix signals from the microphone pgas and the line inputs. the boost stage can provide up to +29db additi onal gain from the microphone pga output to the adc input, providing a total maximum available analogue gain of +59db from microphone to adc. the microphone pga path to the boost mixer is muted using linmute and rinmute as shown in table 4. microphone pga to boost gain settings are shown in table 5. register address bit label default description r32 (20h) adcl signal path 5:4 lmicboost [1:0] 00 left channel input pga boost gain 00 = +0db 01 = +13db 10 = +20db 11 = +29db r33 (21h) adcr signal path 5:4 rmicboost [1:0] 00 right channel input pga boost gain 00 = +0db 01 = +13db 10 = +20db 11 = +29db table 5 microphone pga boost control for line inputs, -12db to +6db gain is available on the boost mixer, with mute control, as shown in table 6. register address bit label default description r43 (2bh) input boost mixer 1 6:4 lin3boost [2:0] 000 linput3 to boost mixer gain 000 = mute 001 = -12db ...3db steps up to 111 = +6db 3:1 lin2boost [2:0] 000 linput2 to boost mixer gain 000 = mute 001 = -12db ...3db steps up to 111 = +6db r44 (2ch) input boost mixer 2 6:4 rin3boost [2:0] 000 rinput3 to boost mixer gain 000 = mute 001 = -12db ...3db steps up to 111 = +6db 3:1 rin2boost [2:0] 000 rinput2 to boost mixer gain 000 = mute 001 = -12db ...3db steps up to 111 = +6db table 6 line input boost control when all three input paths to the boost mixer are disabled, the boost mixer will automatically be muted.
wm8960 production data w pd, october 2011, rev 4.1 24 microphone biasing circuit the micbias output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. refer to the applications information section for recommended external components. the micbias voltage can be altered via the mbsel register bit. when mbsel=0, micbias=0.9*avdd and when mbsel=1, micbias=0.65*avdd. the output can be enabled or disabled using the micb control bit. register address bit label default description r25 (19h) power management (1) 1 micb 0 microphone bias enable 0 = off (high impedance output) 1 = on r48 (30h) additional control (4) 0 mbsel 0 microphone bias voltage control 0 = 0.9 * avdd 1 = 0.65 * avdd table 7 microphone bias control the internal micbias circuitry is shown in figure 9. the maximum source current capability for micbias is 3ma. the external biasing resistors therefore must be large enough to limit the micbias current to 3ma. figure 9 microphone bias schematic
production data wm8960 w pd, october 2011, rev 4.1 25 example input configurations some example input configurations are shown below. single-ended mic configuration on left channel. linput2 and linput3 unused pseudo-differential mic configuration on left channel using linput1 as ground connection and linput2 as signal input. linput3 unused. single-ended mic configuration on left channel. linput2 used as additional input to boost stage. linput3 unused. single-ended mic configuration on left channel. linput3 used as input to bypass path. linput2 unused. figure 10 example microphone input configurations (see also "recommended external components")
wm8960 production data w pd, october 2011, rev 4.1 26 analogue to digital converter (adc) the wm8960 uses stereo 24-bit, 64x oversampled sigma-delta adcs. the use of multi-bit feedback and high oversampling rates reduce the effects of jitter and high frequency noise. the adc full scale input level is proportional to avdd. with a 3.3v supply voltage, the full scale level is 1.0v rms . any voltage greater than full scale may overload the adc and cause distortion. the adcs are enabled by the adcl/r register bit. register address bit label default description r25 (19h) power management (2) 3 adcl 0 enable adc left channel: 0 = adc disabled 1 = adc enabled 2 adcr 0 enable adc right channel: 0 = adc disabled 1 = adc enabled table 8 adc enable control the polarity of the output signal can be changed under software control using the adcpol[1:0] register bits. the datsel bits are used to select which channel is used for the left and right adc data. register address bit label default description r5 (05h) adc and dac control (1) 6:5 adcpol[1:0] 00 adc polarity control: 00 = polarity not inverted 01 = adc l inverted 10 = adc r inverted 11 = adc l and r inverted r23 (17h) additional control (1) 3:2 datsel [1:0] 00 adc data output select 00: left data = left adc; right data =right adc 01: left data = left adc; right data = left adc 10: left data = right adc; right data =right adc 11: left data = right adc; right data = left adc table 9 adc control digital adc volume control the output of the adcs can be digitally amplified or attenuated over a range from ?97db to +30db in 0.5db steps. the volume of each channel can be controlled separately. the gain for a given eight-bit code x is given by: 0.5 ? (x-195) db for 1 ? x ? 255; mute for x = 0 the adcvu control bit controls the loading of digi tal volume control data. when adcvu is set to 0, the ladcvol or radcvol control data will be loaded i nto the respective control register, but will not actually change the digital gain setting. both left and right gain settings are updated when adcvu is set to 1. this makes it possible to update the gain of both channels simultaneously.
production data wm8960 w pd, october 2011, rev 4.1 27 register address bit label default description r21 (15h) left adc digital volume 7:0 ladcvol [7:0] 11000011 ( 0db ) left adc digital volume control 0000 0000 = digital mute 0000 0001 = -97db 0000 0010 = -96.5db ... 0.5db steps up to 1111 1111 = +30db 8 adcvu 0 adc volume update 0 = store ladcvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = ladcvol, right = intermediate latch) r22 (16h) right adc digital volume 7:0 radcvol [7:0] 11000011 ( 0db ) right adc digital volume control 0000 0000 = digital mute 0000 0001 = -97db 0000 0010 = -96.5db ... 0.5db steps up to 1111 1111 = +30db 8 adcvu 0 adc volume update 0 = store radcvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = intermediate latch, right = radcvol) table 10 adc digital volume control adc digital filters the adc filters perform true 24-bit signal processing to convert the raw multi-bit oversampled data from the adc to the correct sampling frequency to be output on the digital audio interface. high pass filter a digital high pass filter is applied by default to the adc path to remove dc offsets. this filter can be disabled using the adchpd register bit. register address bit label default description r5 (05h) adc and dac control (1) 0 adchpd 0 adc high pass filter disable 0 = enable high pass filter on left and right channels 1 = disable high pass filter on left and right channels table 11 adc high pass filter the high pass filter characteristics are shown in the digital filter characteristics section.
wm8960 production data w pd, october 2011, rev 4.1 28 automatic level control (alc) the wm8960 has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. this is ac hieved by continuously adjusting the pga gain so that the signal level at the adc input remains constant. a digital peak detector monitors the adc output and changes the pga gain if necessary. note th at when the alc function is enabled, the settings of registers 0 and 1 (linvol, ipvu, lizc, linmu te, rinvol, rizc and rinmute) are ignored. hold time decay time attack time input signal signal after alc pga gain alc target level figure 11 alc operation the alc function is enabled using the alcsel control bits. when enabled, the recording volume can be programmed between ?1.5db and ?22.5db (relative to adc full scale) using the alcl register bits. an upper limit for the pga gain can be imposed by setting the maxgain control bits. hld, dcy and atk control the hold, decay and attack times, respectively: hold time is the time delay between the peak level detected being below target and the pga gain beginning to ramp up. it can be programmed in power-of-two (2 n ) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7s. alternatively, the hold time can also be set to zero. the hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. decay (gain ramp-up) time is the time that it takes for the pga gain to ramp up across 90% of its range (e.g. from ?15b up to 27.75db). the time it takes for the recording level to return to its target value therefore depends on both the decay time and on the gain adjustment required. if the gain adjustment is small, it will be shorter than the decay time. the decay time can be programmed in power-of-two (2 n ) steps, from 24ms, 48ms, 96ms, etc. to 24.58s. attack (gain ramp-down) time is the time that it takes for the pga gain to ramp down across 90% of its range (e.g. from 27.75db down to -15b gain). the time it takes for the recording level to return to its target value therefore depends on both the attack time and on the gain adjustment required. if the gain adjustment is small, it will be shorter than the attack time. the attack time can be programmed in power-of-two (2 n ) steps, from 6ms, 12ms, 24ms, etc. to 6.14s. when operating in stereo, the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right pgas, so that the stereo image is preserved. however, the alc function can also be enabled on one channel only. in this case, only one pga is controlled by the alc mechanism, while the other channel runs independently with its pga gain set through the control register. when one adc channel is unused, the peak detector disregards that channel.
production data wm8960 w pd, october 2011, rev 4.1 29 register address bit label default description r17 (11h) alc control (1) 8:7 alcsel [1:0] 00 (off) alc function select 00 = alc off (pga gain set by register) 01 = right channel only 10 = left channel only 11 = stereo (pga registers unused) note: ensure that linvol and rinvol settings (reg. 0 and 1) are the same before entering this mode. 6:4 maxgain [2:0] 111 (+30db) set maximum gain of pga 111 : +30db 110 : +24db ?.(-6db steps) 001 : -6db 000 : -12db 3:0 alcl [3:0] 1011 (-12db) alc target (sets signal level at adc input) 0000 = -22.5db fs 0001 = -21.0db fs ? (1.5db steps) 1101 = -3.0db fs 1110 = -1.5db fs 1111 = -1.5db fs r18 (12h) alc control (2) 6:4 mingain [2:0] 000 set minimum gain of pga 000 = -17.25db 001 = -11.25db 010 = -5.25db 011 = +0.75db 100 = +6.75db 101 = +12.75db 110 = +18.75db 111 = +24.75db 3:0 hld [3:0] 0000 (0ms) alc hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ? (time doubles with every step) 1111 = 43.691s r19 (13h) alc control (3) 8 alcmode 0 determines the alc mode of operation: 0 = alc mode 1 = limiter mode 7:4 dcy [3:0] 0011 (192ms) alc decay (gain ramp-up) time 0000 = 24ms 0001 = 48ms 0010 = 96ms ? (time doubles with every step) 1010 or higher = 24.58s 3:0 atk [3:0] 0010 (24ms) alc attack (gain ramp-down) time 0000 = 6ms 0001 = 12ms 0010 = 24ms ? (time doubles with every step) 1010 or higher = 6.14s
wm8960 production data w pd, october 2011, rev 4.1 30 register address bit label default description r27 (1bh) additional control (3) 2:0 adc_alc_sr [2:0] 000 alc sample rate 000 = 44.1k / 48k 001 = 32k 010 = 22.05k / 24k 011 = 16k 100 = 11.25k / 12k 101 = 8k 110 and 111 = reserved table 12 alc control alc sample rate control the register bits adc_alc_sr must be set correctly to ensure that the alc attack, decay and hold times are correct for the chosen sample rate as shown in table 12. peak limiter to prevent clipping when a large signal occurs just after a period of quiet, the alc circuit includes a limiter function. if the adc input signal exceeds 87.5% of full scale (?1.16db), the pga gain is ramped down at the maximum attack rate (as when atk = 0000), until the signal level falls below 87.5% of full scale. this function is automatically enabled whenever the alc is enabled. note: if atk = 0000, then the limiter makes no difference to the operation of the alc. it is designed to prevent clipping when long attack times are used. noise gate when the signal is very quiet and consists mainly of noise, the alc function may cause ?noise pumping?, i.e. loud hissing noise during silence periods. the wm8960 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, ngth. the noise gate cuts in when: ? signal level at adc [db] < ngth [db] + pga gain [db] + mic boost gain [db] this is equivalent to: ? signal level at input pin [db] < ngth [db] the pga gain will then be held constant (preventing it from ramping up as it normally would when the signal is quiet). the table below summarises the noise gate control register. the ngth control bits set the noise gate threshold with respect to the adc full-scale range. the threshold is adjusted in 1.5db steps. levels at the extremes of the range may cause inappropriate operation, so care should be taken with set?up of the function. note that the noise gate only works in conjunction with the alc function, and always operates on the same channel(s) as the alc (left, right, both, or none). register address bit label default description r20 (14h) noise gate control 7:3 ngth [4:0] 00000 noise gate threshold 00000 -76.5dbfs 00001 -75dbfs ? 1.5 db steps 11110 -31.5dbfs 11111 -30dbfs 0 ngat 0 noise gate function enable 0 = disable 1 = enable table 13 noise gate control
production data wm8960 w pd, october 2011, rev 4.1 31 output signal path the hi-fi dacs and dac digital filters are enabled by register bits dacl and dacr. the mixers and output drivers can be separately enabled by individual c ontrol bits (see analogue outputs). thus it is possible to utilise the analogue mixing and amplification provided by the wm8960, irrespective of whether the dacs are enabled or not. the wm8960 dacs receive digital input data on the dacd at pin. the digital filter block processes the data to provide the following functions: ? digital volume control with soft mute and soft un-mute ? mono mix ? 3d stereo enhancement ? de-emphasis ? sigma-delta modulation high performance sigma-delta 24-bit audio dac converts the digital data into an analogue signal. the analogue outputs from the dacs can then be mixed with the analogue line inputs and the adc analogue inputs. this mix is fed to the output drivers for headphone or speaker output. out3 can provide a mono mix of left and right mixers or a pseudo-ground for capless headphone drive. digital playback (dac) path digital data is passed to the wm8960 via the flexible audio interface to the hi-fi dacs. the dacs are enabled by the dacl and dacr register bits. register address bit label default description r26 (1ah) power management (2) 8 dacl 0 left channel dac enable 0 = dac disabled 1 = dac enabled 7 dacr 0 right channel dac enable 0 = dac disabled 1 = dac enabled table 14 dac enable control digital dac volume control the signal volume from each dac can be controlled digitally, in the same way as the adc volume (see digital adc volume control). the gain and attenuation range is ?127db to 0db in 0.5db steps. the level of attenuation for an eight-bit code x is given by: 0.5 ? (x-255) db for 1 ? x ? 255; mute for x = 0 the dacvu control bit controls the loading of digi tal volume control data. when dacvu is set to 0, the ldacvol or rdacvol control data is loaded into an intermediate register, but the actual gain does not change. both left and right gain settings are updated simultaneously when dacvu is set to 1. see "volume updates" for more information on volume update bits.
wm8960 production data w pd, october 2011, rev 4.1 32 register address bit label default description r10 (0ah) left channel digital volume 8 dacvu 0 dac volume update 0 = store ldacvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = ldacvol, right = intermediate latch) 7:0 ldacvol [7:0] 11111111 ( 0db ) left dac digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db r11 (0bh) right channel digital volume 8 dacvu 0 dac volume update 0 = store rdacvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = intermediate latch, right = rdacvol) 7:0 rdacvol [7:0] 11111111 ( 0db ) right dac digital volume control similar to ldacvol table 15 digital volume control dac soft mute and soft un-mute the wm8960 also has a soft mute function, which, when enabled, gradually attenuates the volume of the digital signal to zero. when soft mute is disabled, the gain will either gradually ramp back up to the digital gain setting, or return instantly to the digital gain setting, depending on the dacsmm register bit. the dac is soft-muted by default. to play back an audio signal, this function must first be disabled by setting the dacmu bit to zero. dacsmm would typically be enabled when using soft mute during playback of audio data so that when soft mute is then disabled, the sudden volume increase will not create pop noise by jumping immediately to the previous volume level (e.g. resuming playback after pausing during a track). dacsmm would typically be disabled when un-muting at the start of a digital music file, so that the first part of the track is not attenuated (e.g. when starting playback of a new track, or resuming playback after pausing between tracks). dac muting and un-muting using volume control bits ldacvol and rdacvol. dac muting and un-muting using soft mute bit dacmu. soft un-mute not enabled (dacsmm = 0). dac muting and un-muting using soft mute bit dacmu. soft un-mute enabled (dacsmm = 1). figure 12 dac mute control the volume ramp rate during soft mute and un-mute is controlled by the dacmr bit. ramp rates of fs/32 and fs/2 are selectable as shown in table 16 (fs = dac sample rate).
production data wm8960 w pd, october 2011, rev 4.1 33 register address bit label default description r5 (05h) adc and dac control (1) 3 dacmu 1 digital soft mute 1 = mute 0 = no mute (signal active) r6 (06h) adc and dac control (2) 3 dacsmm 0 dac soft mute mode 0 = disabling soft-mute (dacmu=0) will cause the volume to change immediately to the ldacvol / rdacvol settings 1 = disabling soft-mute (dacmu=0) will cause the volume to ramp up gradually to the ldacvol / rdacvol settings 2 dacmr 0 dac soft mute ramp rate 0 = fast ramp (fs/2 at fs=48k, providing maximum delay of 10.7ms) 1 = slow ramp (fs/32 at fs=48k, providing maximum delay of 171ms) table 16 dac soft-mute control dac de-emphasis digital de-emphasis can be applied to the dac playback data (e.g. when the data comes from a cd with pre-emphasis used in the recording). de-emphasis filtering is available for sample rates of 48khz, 44.1khz and 32khz. register address bit label default description r5 (05h) adc and dac control (1) 2:1 deemph [1:0] 00 de-emphasis control 11 = 48khz sample rate 10 = 44.1khz sample rate 01 = 32khz sample rate 00 = no de-emphasis table 17 dac de-emphasis control dac output phase and mono mixing the digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. the bitstream data enters two multi-bit, sigma-delta dacs, which convert them to high quality analogue audio signals. the multi-bit dac architecture reduces high frequency noise and sensitivity to clock jitter. it also uses a dyna mic element matching technique for high linearity and low distortion. in normal operation, the left and right channel digital audio data is converted to analogue in two separate dacs. there is a mono-mix mode where the two audio channels are mixed together digitally and then converted to analogue using only one dac, while the other dac is switched off. the mono- mix signal can be selected to appear on both analogue output channels. the mono mix is automatically attenuated by 6db to prevent clipping. the dac output defaults to non-inverted. setting dacpol[0] bit will invert the left dac output phase and setting dacpol[1] bit will invert the right dac output phase.
wm8960 production data w pd, october 2011, rev 4.1 34 register address bit label default description r6 (06h) adc and dac control (2) 6:5 dacpol[1:0] 00 dac polarity control: 00 = polarity not inverted 01 = dac l inverted 10 = dac r inverted 11 = dac l and r inverted r23 (17h) additional control (1) 4 dmonomix 0 dac mono mix 0 = stereo 1 = mono (mono mix output on enabled dacs) table 18 dac mono mix and phase invert select 3d stereo enhancement the wm8960 has a digital 3d enhancement option to artificially increase the separation between the left and right channels. this effect can only be used for playback, not for record. the 3d enhancement function is activated by the 3den bit, and the 3ddepth setting controls the degree of stereo expansion. additionally, one of four filter characteristics can be selected for the 3d processing, using the 3duc and 3dlc control bits. register address bit label default description r16 (10h) 3d enhance 6 3duc 0 upper cut-off frequency 0 = high (recommended for fs>=32khz) 1 = low (recommended for fs<32khz) 5 3dlc 0 lower cut-off frequency 0 = low (recommended for fs>=32khz) 1 = high (recommended for fs<32khz) 4:1 3ddepth [3:0] 0000 3d stereo depth 0000 = 0% (minimum 3d effect) 0001 = 6.67% .... 1110 = 93.3% 1111 = 100% (maximum 3d effect) 0 3den 0 3d stereo enhancement enable 0 = disabled 1 = enabled table 19 3d stereo enhancement function when 3d enhancement is enabled it may be necessary to attenuate the signal by 6db to avoid limiting. this is a user-selectabl e function, enabled by setting dacdiv2. register address bit label default description r5 (05h) adc and dac control (1) 7 dacdiv2 0 dac 6db attenuate enable 0 = disabled (0db) 1 = -6db enabled table 20 dac 6db attenuation select
production data wm8960 w pd, october 2011, rev 4.1 35 output mixers left and right analogue mixers allow the dac output and analogue bypass paths to be mixed. programmable attenuation and mute is available on the analogue bypass paths from linput3, rinput3 and from the input boost mixers as shown in figure 13. a mono mix of left and right output mixers is also available on out3. figure 13 output mixer path left and right mixers are enabled by the lomix and romix register bits. the mono mixer is enabled by out3 register bit, which also enables the out3 driver. register address bit label default description r47 (2fh) power management (3) 3 lomix 0 left output mixer enable control 0 = disabled 1 = enabled 4 romix 0 right output mixer enable control 0 = disabled 1 = enabled r26 (1ah) power management (2) 1 out3 0 mono output and mono mixer enable control 0 = mono mixer and output disabled 1 = mono mixer and output enabled table 21 output mixer enable control inputs to the mixers from the dac and bypass paths can be individually muted. the bypass paths have programmable attenuation as shown in table 22. to prevent pop noise, it is recommended not to change volume levels of these paths during playback.
wm8960 production data w pd, october 2011, rev 4.1 36 register address bit label default description r34 (22h) left output mixer control 8 ld2lo 0 left dac to left output mixer 0 = disable (mute) 1 = enable path 7 li2lo 0 linput3 to left output mixer 0 = disable (mute) 1 = enable path 6:4 li2lovol [2:0] 101 (-15db) linput3 to left output mixer volume 000 = 0db ...(3db steps) 111 = -21db r45 (2dh) bypass (1) 7 lb2lo 0 left input boost mixer to left output mixer 0 = disable (mute) 1 = enable path 6:4 lb2lovol [2:0] 101 (-15db) left input boost mixer to left output mixer volume 000 = 0db ...(3db steps) 111 = -21db r37 (25h) right output mixer control 8 rd2ro 0 right dac to right output mixer 0 = disable (mute) 1 = enable path 7 ri2ro 0 rinput3 to right output mixer 0 = disable (mute) 1 = enable path 6:4 ri2rovol [2:0] 101 (-15db) rinput3 to right output mixer volume 000 = 0db ...(3db steps) 111 = -21db r46 (2eh) bypass (2) 7 rb2ro 0 right input boost mixer to right output mixer 0 = disable (mute) 1 = enable path 6:4 rb2rovol [2:0] 101 (-15db) right input boost mixer to right output mixer volume 000 = 0db ...(3db steps) 111 = -21db table 22 left and right output mixer mute and volume control the mono output mixer can output, left, right, left+right or a buffered vmid. 0db or 6db attenuation is selectable using moutvol register bit. it is recommended to attenuate a mono mix of left and right channels by 6db in order to prevent clipping. this attenuation control (moutvol) should not be modified while out3 is enabled as this may cause an audible click noise.
production data wm8960 w pd, october 2011, rev 4.1 37 register address bit label default description r38 (26h) mono out mix (1) 7 l2mo 0 left output mixer to mono output mixer control 0 = left channel mix disabled 1 = left channel mix enabled r39 (27h) mono out mix (2) 7 r2mo 0 right output mixer to mono output mixer control 0 = right channel mix disabled 1 = right channel mix enabled r42 (2ah) mono out volume 6 moutvol 1 mono output mixer volume control 0 = 0db 1 = -6db table 23 output mixer enable control when left and right inputs to the mono mixer are both disabled, the mono mixer will output vmid. analogue outputs hp_l and hp_r outputs the hp_l and hp_r pins can drive a 16 ? or 32 ? headphone or a line output (see headphone output and line output sections, respectively). the signal volume on hp_l and hp_r can be independently adjusted under software control by writing to lout1vol and rout1vol, respectively. note that gains over 0db may cause cli pping if the signal is large. any gain setting below 0101111 (minimum) mutes the output driver. the corresponding output pin remains at the same dc level (the reference voltage on the vref pin), so that no click noise is produced when muting or un- muting. a zero cross detect on the analogue output may also be enabled when changing the gain setting to minimize audible clicks and zipper noise as the gain updates. if zero cross is enabled a timeout is also available to update the gain if a zero cross does not occur. this function may be enabled by setting toen in register r23 (17h). the timeout period is set by toclksel. note: sysclk must be enabled to use this function.
wm8960 production data w pd, october 2011, rev 4.1 38 register address bit label default description r2 (02h) lout1 volume 8 out1vu 0 headphone volume update 0 = store lout1vol in intermediate latch (no gain change) 1 = update left and right channel gains (left = lout1vol, right = intermediate latch) 7 lo1zc 0 left zero cross enable 0 = change gain immediately 1 = change gain on zero cross only 6:0 lout1vol [6:0] 0000000 (mute) lout1 volume 1111111 = +6db ? 1db steps down to 0110000 = -73db 0101111 to 0000000 = analogue mute r3 (03h) rout1 volume 8 out1vu 0 headphone volume update 0 = store rout1vol in intermediate latch (no gain change) 1 = update left and right channel gains (left = intermediate latch, right = rout1vol) 7 ro1zc 0 right zero cross enable 0 = change gain immediately 1 = change gain on zero cross only 6:0 rout1vol [6:0] 0000000 (mute) rout1 volume similar to lout1vol table 24 lout1/rout1 volume control see "volume updates" for more information on volume update bits, zero cross and timeout operation. class d speaker outputs the spk_lp/spk_ln and spk_rp/spk_rn output pins are class d speaker drivers. each pair is independently controlled and can drive an 8 ? btl speaker (see speaker output section). output mixer volume is relative to avdd, while an additional boost stage is available to accommodate higher spkvdd1/spkvdd2 supply voltages. this allows avdd to be run at a lower voltage to save power, while maximum output power can be delivered to the load, utilising the full range of spkvdd1/spkvdd2. note that the btl speaker connect ion provides an additional +6db gain at the output. figure 14 speaker boost operation
production data wm8960 w pd, october 2011, rev 4.1 39 register address bit label default description r40 (28h) left speaker volume 6:0 spklvol [6:0] 0000000 (mute) spk_lp/spk_ln volume 1111111 = +6db ? 1db steps down to 0110000 = -73db 0101111 to 0000000 = analogue mute 7 spklzc 0 left speaker zero cross enable 1 = change gain on zero cross only 0 = change gain immediately 8 spkvu 0 speaker volume update 0 = store spklvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = spklvol, right = intermediate latch) r41 (29h) right speaker volume 6:0 spkrvol [6:0] 0000000 (mute) spk_rp/spk_rn volume 1111111 = +6db ? 1db steps down to 0110000 = -73db 0101111 to 0000000 = analogue mute 7 spkrzc 0 right speaker zero cross enable 1 = change gain on zero cross only 0 = change gain immediately 8 spkvu 0 speaker volume update 0 = store spkrvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = intermediate latch, right = spkrvol) r51 (33h) class d control (3) 5:3 dcgain [2:0] 000 (1.0x) dc speaker boost (boosts speaker dc output level by up to 1.8 x on left and right channels) 000 = 1.00x boost (+0db) 001 = 1.27x boost (+2.1db) 010 = 1.40x boost (+2.9db) 011 = 1.52x boost (+3.6db) 100 = 1.67x boost (+4.5db) 101 = 1.8x boost (+5.1db) 110 to 111 = reserved 2:0 acgain [2:0] 000 (1.0x) ac speaker boost (boosts speaker ac output signal by up to 1.8 x on left and right channels) 000 = 1.00x boost (+0db) 001 = 1.27x boost (+2.1db) 010 = 1.40x boost (+2.9db) 011 = 1.52x boost (+3.6db) 100 = 1.67x boost (+4.5db) 101 = 1.8x boost (+5.1db) 110 to 111 = reserved table 25 spk_l/spk_r volume and speaker boost control to prevent pop noise, dcgain and acgain should not be modified while the speaker outputs are enabled. to avoid clipping at speaker ground, acgain should not be greater than dcgain.
wm8960 production data w pd, october 2011, rev 4.1 40 to avoid clipping at speaker supply, spkvdd1 and spkvdd2 must be high enough to support the peak output voltage when using dcgain and acga in functions. the peak output voltage is avdd*(dcgain+acgain)/2. dcgain should normally be set to the same value as acgain. see "volume updates" for more information on volume update bits, zero cross and timeout operation. see "class d speaker outputs" for more information on class d speaker operation. out3 output the out3 pin can drive a 16 ? or 32 ? headphone or a line output or be used as a pseudo-ground for capless headphone drive (see headphone output section). it can also drive out a mono mix of left and right output mixers (see output signal path).
production data wm8960 w pd, october 2011, rev 4.1 41 enabling the outputs each analogue output of the wm8960 can be independently enabled or disabled. the analogue mixer associated with each output is powered on or off along with the output pin. all outputs are disabled by default. to save power, unused outputs should remain disabled. register address bit label default description r26 (1ah) power management (2) 6 lout1 0 lout1 output enable 5 rout1 0 rout1 output enable 4 spkl 0 spk_lp and spk_ln volume control enable 3 spkr 0 spk_rp and spk_rn volume control enable 1 out3 0 out3 enable r49 (31h) class d control (1) 7:6 spk_op_en [1:0] 00 enable class d speaker outputs 00 = off 01 = left speaker only 10 = right speaker only 11 = left and right speakers enabled note: all ?enable? bits are 1 = on, 0 = off table 26 analogue output control the speaker output enable bits spk_op_en[1:0] should not be enabled until there is a valid switching clock to drive the class d outputs. this means that sysclk must be active, and dclkdiv set to an appropriate value to produce a class d clock of between 700khz and 800khz for best performance (see "class d speaker outputs" and "clocking and sample rates" sections for more information). whenever an analogue output is disabled, it remains connected to vref through a resistor. this helps to prevent pop noise when the output is re-enabled. the resistance between vref and each output can be controlled using the vroi bit in register 27. if a high impedance is desired for disabled outputs, vroi can then be set to 1, increasing the resistance to about 20k ? . register address bit label default description r27 (1bh) additional (1) 6 vroi 0 vref to analogue output resistance (disabled outputs) 0 = 500 ? vmid to output 1 = 20k ? vmid to output table 27 disabled outputs to vref resistance headphone output analogue outputs hp_l/hp_r, and out3, can drive a 16 ? or 32 ? headphone load, either through dc blocking capacitors, or dc coupled without any capacitor. headphone output using dc blocking capacitors dc coupled headphone output (l2mo=0; r2mo=0) figure 15 recommended headphone output configurations
wm8960 production data w pd, october 2011, rev 4.1 42 when dc blocking capacitors are used, then their capacitance and the load resistance together determine the lower cut-off frequency, f c . increasing the capacitance lowers f c , improving the bass response. smaller capacitance values will diminish the bass response. assuming a 32 ? load and c1, c2 = 100 ? f: f c = 1 / 2 ? r l c 1 = 1 / (2 ? x 32 ? x 100 ? f) = 50 hz in the dc coupled configuration, the headphone ?ground? is connected to the out3 pin, which must be enabled by setting out3 = 1 and muted by setting l2mo=0 and r2mo=0. as the out3 pin produces a dc voltage of avdd/2 (=vref), ther e is no dc offset between hp_l/hp_r and out3, and therefore no dc blocking capacitors are required. this saves space and material cost in portable applications. it is recommended to connect the dc coupled headphone outputs only to headphones, and not to the line input of another device. although the built-in short circuit protection will prevent any damage to the headphone outputs, such a connection may be noisy, and may not function properly if the other device is grounded. class d speaker outputs the class d speaker outputs spk_ln/spk_lp and spk_rn/spk_rp can drive 1w into 8 ? btl speakers. class d outputs reduce power consumption and maximise efficiency by reducing power dissipated in the output drivers, delivering most of the power directly to the load. this is achieved by pulse width modulation (pwm) of a high frequency square wave, allowing the audio signal level to be set by controlling the pulse width. the frequency of the output waveform is controlled by dclkdiv, and is derived from sysclk. when the speakers are close to the device (typically less than about 100mm), the internal filtering effects of the speaker can be used. where signals are routed over longer distances, it is recommended to use additional passive filtering, positioned close to the wm8960, to reduce emi. see "applications information" for more information on emi reduction. register address bit label default description r8 (08h) clocking (2) 8:6 dclkdiv 111 controls clock division from sysclk to generate suitable class d clock. 000 = sysclk / 1.5 001 = sysclk / 2 010 = sysclk / 3 011 = sysclk / 4 100 = sysclk / 6 101 = sysclk / 8 110 = sysclk / 12 111 = sysclk / 16 r49 (31h) class d control (1) 7:6 spk_op_en [1:0] 00 enable class d speaker outputs 00 = off 01 = left speaker only 10 = right speaker only 11 = left and right speakers enabled table 28 class d control registers the class d outputs require a pwm switching clock, which is derived from sysclk. this clock should not be altered or disabled while the class d outputs are enabled. see "clocking and sample rates" for more information.
production data wm8960 w pd, october 2011, rev 4.1 43 volume updates volume settings will not be applied to input or output pgas until a '1' is written to one of the update bits (ipvu, out1vu, spkvu bits). this is to allow left and right channels to be updated at the same time, as shown in figure 16. figure 16 simultaneous left and right volume updates if the volume is adjusted while the signal is a non-zero value, an audible click can occur as shown in figure 17. figure 17 click noise during volume update in order to prevent this click noise, a zero cross function is provided. when enabled, this will cause the pga volume to update only when a zero crossing occurs, minimising click noise as shown in figure 18.
wm8960 production data w pd, october 2011, rev 4.1 44 figure 18 volume update using zero cross detection if there is a long period where no zero-crossing occurs, a timeout circuit in the wm8960 will automatically update the volume. the volume updates will occur between one and two timeout periods, depending on when the volume update bit is set as shown in figure 19. the toen register bit must be set to enable this timeout function. the timeout period is set by toclksel. figure 19 volume update after timeout
production data wm8960 w pd, october 2011, rev 4.1 45 headphone jack detect the adclrc/gpio1, linput3/jd2 and rinput3/jd3 pins can be selected as headphone jack detect inputs to automatically disable the speaker output and enable the headphone output e.g. when a headphone is plugged into a jack socket. in this mode, enabled by setting hpswen, the headphone detect input pin switches between headphone and speaker outputs (e.g. when the pin is connected to a mechanical switch in the headphone socket to detect plug-in). the hpsel[1:0] bits select the input pin used for this function. the hpsw pol bit reverses the pin?s polarity. note that the lout1, rout1, spkl and spkr bits in register 26 must also be set for headphone and speaker output (see table 29 and table 30). toen must also be set to enable the clock which is used for de-bouncing the jack detect input. toclksel selects a fast or slow de-bounce period. note that sysclk must be enabled to use this function. when using capless mode, the out3cap bit should be enabled so that out3 is enabled/disabled at the same time as hp_l and hp_r to prevent pop noise. the debounced headphone detect signal can also be output to the adclrc/gpio1 pin (see gpio section). this function is not available when using gpio1 as an input or as adclrc. when using the adclrc/gpio1 pin as a headphone detect input, the alrcgpio register bit needs to be set to 1. in this mode, daclrc is used for both adc and dac frame clocks. (see gpio section for more information) note: when linput3 or rinput3 is used as the headphone detect input, the thresholds become cmos levels (0.3 avdd / 0.7 avdd). hpswen hpswpol headphone detect pin (linput3/jd2, rinput3/jd3 or adclrc/gpio1) l/rout1 (and out3 in capless mode) (reg. 26) spkl/r (reg. 26) headphone enabled (and out3 in capless mode) speaker enabled 0 x x 0 0 no no 0 x x 0 1 no yes 0 x x 1 0 yes no 0 x x 1 1 yes yes 1 0 0 x 0 no no 1 0 0 x 1 no yes 1 0 1 0 x no no 1 0 1 1 x yes no 1 1 0 0 x no no 1 1 0 1 x yes no 1 1 1 x 0 no no 1 1 1 x 1 no yes table 29 headphone jack detect operation register address bit label default description r24 (18h) additional control (2) 6 hpswen 0 headphone switch enable 0 = headphone switch disabled 1 = headphone switch enabled 5 hpswpol 0 headphone switch polarity 0 = hpdetect high = headphone 1 = hpdetect high = speaker
wm8960 production data w pd, october 2011, rev 4.1 46 register address bit label default description r27 (1bh) additional control (3) 3 out3cap 0 capless mode headphone switch enable 0 = out3 unaffected by jack detect events 1 = out3 enabled and disabled together with hp_l and hp_r in response to jack detect events r48 (30h) additional control (4) 3:2 hpsel[1:0] 00 headphone switch input select 0x = gpio1 used for jack detect input (requires adclrc pin to be configured as a gpio) 10 = jd2 used for jack detect input 11 = jd3 used for jack detect input r23 (17h) additional control (1) 0 toen 0 slow clock enable (must be enabled for jack detect de-bounce) 0 = slow clock disabled 1 = slow clock enabled 1 toclksel 0 slow clock selection (used for volume update timeouts and for jack detect debounce) 0 = sysclk / 2 21 (slower response) 1 = sysclk / 2 19 (faster response) table 30 headphone jack detect figure 20 example headset detection circuit using normally-open switch figure 21 example headset detection circuit using normally-closed switch thermal shutdown the speaker and headphone outputs can drive very large currents. to protect the wm8960 from overheating a thermal shutdown circuit is included and is enabled by default. if the device temperature reaches approximately 150 0 c and the thermal shutdown circuit is enabled (tsden = 1; tsensen = 1) the speaker and headphone amplifie rs (hp_l, hp_r, spk_lp, spk_ln, spk_rp, spk_rn and out3) will be disabled. this feature can be disabled to save power when the device is in standby mode. tsensen must be set to 1 to enable the temperature sensor when using the tsden thermal shutdown function. the output of the temperature sensor can also be output to the gpio1 pin.
production data wm8960 w pd, october 2011, rev 4.1 47 register address bit label default description r23 (17h) additional control (1) 8 tsden 1 thermal shutdown enable 0 = thermal shutdown disabled 1 = thermal shutdown enabled (tsensen must be enabled for this function to work) r48 (30h) additional control (4) 1 tsensen 1 temperature sensor enable 0 = temperature sensor disabled 1 = temperature sensor enabled table 31 thermal shutdown general purpose input/output the wm8960 has three dual purpose input/output pins. ? linput3/jd2: analogue input or headphone detect input. ? rinput3/jd3: analogue input or headphone detect input. ? adclrc/gpio1: adc left/right frame clock or gpio pin. the adclrc/gpio1 pin can be configured as a left/right frame clock for the adc, a headphone detect input, or one of a number of gpio output functions as shown in table 32. the default configuration for the linput3 and rinput2 pins is to be analogue inputs. the default configuration for the adclrc/gpio1 pin is to be the adc left/right frame clock. register address bit label default description r9 (09h) audio interface (2) 6 alrcgpio 0 adclrc/gpio1 pin function select 0 = adclrc frame clock for adc 1 = gpio pin r48 (30h) additional control (4) 6:4 gpiosel [2:0] 000 adclrc/gpio1 gpio function select: 000 = jack detect input 001 = reserved 010 = temperature ok 011 = debounced jack detect output 100 = sysclk output 101 = pll lock 110 = logic 0 111 = logic 1 7 gpiopol 0 gpio polarity invert 0 = non inverted 1 = inverted r52 (34h) clocking (2) 8:6 opclkdiv [2:0] 000 sysclk output to gpio clock division ratio 000 = sysclk 001 = sysclk / 2 010 = sysclk / 3 011 = sysclk / 4 100 = sysclk / 5.5 101 = sysclk / 6 table 32 gpio control slow clock must be enabled (toen = 1) when using the jack detect function. this slow clock is used to debounce the jack detect input. the debounce period can be selected using toclksel. the temperature sensor must be enabled for the "temperature ok" gpio output to function properly.
wm8960 production data w pd, october 2011, rev 4.1 48 for further details of the jack detect operation see the headphone switch section. digital audio interface the digital audio interface is used for inputting dac data into the wm8960 and outputting adc data from it. it uses five pins: ? adcdat: adc data output ? adclrc: adc data alignment clock ? dacdat: dac data input ? daclrc: dac data alignment clock ? bclk: bit clock, for synchronisation the clock signals bclk, adclrc and dacl rc can be outputs when the wm8960 operates as a master, or inputs when it is a slave (see master and slave mode operation, below). adclrc can also be configured as a gpio pin. in this case, the adc will use daclrc as a frame clock. the adclrc/gpio1 pin function should not be modified while the adc is enabled. four different audio data formats are supported: ? left justified ? right justified ? i 2 s ? dsp mode all four of these modes are msb first. they are described in audio data formats, below. refer to the electrical characteristic section for timing information. master and slave mode operation the wm8960 can be configured as either a master or slave mode device. as a master device the wm8960 generates bclk, adclrc and daclrc and thus controls sequencing of the data transfer on adcdat and dacda t. in slave mode, the wm8960 responds with data to clocks it receives over the digital audio interface. the mode can be selected by writing to the ms bit. master and slave modes are illustrated below. figure 22 master mode figure 23 slave mode operation with adclrc as gpio when alrcgpio=1, the daclrc pin is used as a frame clock for adcs and dacs as shown below. the adcs and dacs must operate at the same sample rate in this mode. see table 32 for details of gpio pin configuration. figure 24 master mode with adclrc as gpio figure 25 slave mode with adclrc as gpio bclk a dcdat a dclrc dacdat daclrc wm8960 codec dsp encoder/ decoder note: the adc and dac can run at different sample rates bcl k a dcdat a dclrc dacdat daclrc wm8960 codec dsp encoder/ decoder note: the adc and dac can run at different sample rates
production data wm8960 w pd, october 2011, rev 4.1 49 bclk divide the bclk frequency in master mode is contro lled by bclkdiv[3:0]. when the adcs and dacs are operating at different sample rates, bclkdiv must be set appropriately to support the data rate of whichever is the faster. internal clock divide and phase control mechanisms ensure that the bclk, adclrc and daclrc edges will occur in a predictable and repeatable position relative to each other and to the data for a given combination of dac sample rate, adc sample rate and bclkdiv settings. see clocking and sample rates section for more information. audio data formats in left justified mode, the msb is available on the first rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrclk transition. figure 26 left justified audio interface (assuming n-bit word length) in right justified mode, the lsb is available on the last rising edge of bclk before a lrclk transition. all other bits are transmitted befor e (msb first). depending on word length, bclk frequency and sample rate, there may be unused bclk cycles after each lrclk transition. figure 27 right justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second ri sing edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next.
wm8960 production data w pd, october 2011, rev 4.1 50 figure 28 i 2 s justified audio interface (assuming n-bit word length) in dsp/pcm mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk (selectable by lrp) following a rising edge of lrc. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. in device master mode, the lrc output will resemble the frame pulse shown in figure 29 and figure 30. in device slave mode, figure 31 and figure 32, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one bclk period before the rising edge of the next frame pulse. figure 29 dsp/pcm mode audio interface (mode a, lrp=0, master) figure 30 dsp/pcm mode audio interface (mode b, lrp=1, master)
production data wm8960 w pd, october 2011, rev 4.1 51 figure 31 dsp/pcm mode audio interface (mode a, lrp=0, slave) figure 32 dsp/pcm mode audio interface (mode b, lrp=1, slave)
wm8960 production data w pd, october 2011, rev 4.1 52 audio interface control the register bits controlling audio format, word length and master / slave mode are summarised in table 33. ms selects audio interface operation in master or slave mode. in master mode bclk, adclrc and daclrc are outputs. the frequency of adclrc and daclrc is set by the bits adcdiv and dacdiv and the frequency of bclk is s et by the bits bclkdiv (see "clocking and sample rates"). in slave mode bc lk, adclrc and daclrc are inputs. register address bit label default description r7 (07h) digital audio interface format 8 alrswap 0 left/right adc channel swap 1 = swap left and right adc data in audio interface 0 = output left and right data as normal 7 bclkinv 0 bclk invert bit (for master and slave modes) 0 = bclk not inverted 1 = bclk inverted 6 ms 0 master / slave mode control 0 = enable slave mode 1 = enable master mode 5 dlrswap 0 left/right dac channel swap 0 = output left and right data as normal 1 = swap left and right dac data in audio interface 4 lrp 0 right, left and i 2 s modes ? lrclk polarity 0 = normal lrclk polarity 1 = invert lrclk polarity dsp mode ? mode a/b select 0 = msb is available on 2nd bclk rising edge after lrc rising edge (mode a) 1 = msb is available on 1st bclk rising edge after lrc rising edge (mode b) 3:2 wl[1:0] 10 audio data word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits (see note) 1:0 format[1:0] 10 audio data format select 00 = right justified 01 = left justified 10 = i 2 s format 11 = dsp mode table 33 audio data format control note: right justified mode does not support 32-bit data.
production data wm8960 w pd, october 2011, rev 4.1 53 audio interface output tristate register bit tris, register 24(18h) bit[3] can be used to tristate the adcdat pin and switch adclrc, daclrc and bclk to inputs. in slave mode (ms=0) adclrc, daclrc and bclk are by default configured as inputs and only adcdat will be tri-stated, (see table 34). when the adclrc/gpio1 pin is configured as a gpio, this pin will not be tristated by the tris register bit. register address bit label default description r24 (18h) additional control (2) 3 tris 0 tristates adcdat and switches adclrc, daclrc and bclk to inputs. 0 = adcdat is an output; adclrc, daclrc and bclk are inputs (slave mode) or outputs (master mode) 1 = adcdat is tristated; daclrc and bclk are inputs; adclrc is an input (when not configured as a gpio) table 34 tri-stating the audio interface master mode adclrc and daclrc enable in master mode, by default adclrc clock generator is disabled and will output a logic 0 when the adcs are both disabled and daclrc clock generator is disabled and will output a logic 0 when the dacs are both disabled. register bit lrcm, register 24 (18h) bit[2] changes the control so that the adclrc and daclrc clock generators are both disabled only when both adcs and both dacs are disabled. this enables the user to use e.g. adclrc for both adc and dac lrclk and disable the adc when dac only operation is required, (see table 35). when adclrc is configured as a gpio (using alrcgpio), daclrc is used for the adcs and the dacs and will only be disabled in master m ode when both adcs and both dacs are disabled. figure 33 master mode clock output control
wm8960 production data w pd, october 2011, rev 4.1 54 register address bit label default description r24 (18h) additional control (2) 2 lrcm 0 selects disable mode for adclrc and daclrc (master mode) 0 = adclrc disabled when adc (left and right) disabled; daclrc disabled when dac (left and right) disabled. 1 = adclrc and daclrc disabled only when adc (left and right) and dac (left and right) are disabled. table 35 adclrc/daclrc enable companding the wm8960 supports a-law and ? -law companding on both transmit (adc) and receive (dac) sides. companding can be enabled on the dac or adc audio interfaces by writing the appropriate value to the daccomp or adccomp register bits respectively. register address bit label default description r9 (09h) audio interface (2) 2:1 adccomp 00 adc companding 00 = off 01 = reserved 10 = -law 11 = a-law 4:3 daccomp 00 dac companding 00 = off 01 = reserved 10 = -law 11 = a-law 5 wl8 0 0 = off 1 = device operates in 8-bit mode. table 36 companding control companding involves using a piecewise linear approximation of the following equations (as set out by itu-t g.711 standard) for data compression: ? -law (where ? =255 for the u.s. and japan): f(x) = ln( 1 + ? |x|) / ln( 1 + ? ) -1 x 1 a-law (where a=87.6 for europe): f(x) = a|x| / ( 1 + lna) ? for x 1/a f(x) = ( 1 + lna|x|) / (1 + lna) ? for 1/a x 1 the companded data is also inverted as recommended by the g.711 standard (all 8 bits are inverted for ? -law, all even data bits are inverted for a-law). the data will be transmitted as the first 8 msb?s of data. companding converts 13 bits ( ? -law) or 12 bits (a-law) to 8 bits using non-linear quantization. the input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. this is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. the companded signal is an 8-bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits). setting the wl8 register bit allows the device to operate with 8-bit data. in this mode it is possible to use 8 bclk cycles per lrc frame. when using dsp mode b, this allows 8-bit data words to be output consecutively every 8 bclk cycles and can be used with 8-bit data words using the a-law and u-law companding functions.
production data wm8960 w pd, october 2011, rev 4.1 55 bit7 bit[6:4] bit[3:0] sign exponent mantissa table 37 8-bit companded word composition u-law companding 0 20 40 60 80 100 120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 34 -law companding a-law companding 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 35 a-law companding
wm8960 production data w pd, october 2011, rev 4.1 56 loopback setting the loopback register bit enables digital loopback. when this bit is set the output data from the adc audio interface is fed directly into the dac data input. the adcs and dacs must both use daclrc w hen loopback is enabled. this is enabled by setting register bit alrcgpio = 1. register address bit label default description r9 audio interface 0 loopback 0 digital loopback function 0 = no loopback. 1 = loopback enabled, adc data output is fed directly into dac data input. table 38 loopback control clocking and sample rates figure 36 clocking scheme clocks for the adcs and dacs, the dsp core functi ons, the digital audio interface and the class d outputs are all derived from sysclk as show in figure 36.
production data wm8960 w pd, october 2011, rev 4.1 57 sysclk can either be derived directly from mclk, or generated from a pll using mclk as a reference. the clock source is selected by clksel. many commonly-used audio sample rates can be derived directly from mclk, while the pll provides additional flexibility. the adc and dac sample rates are independently selectable, relative to sysclk, using adcdiv and dacdiv. in master mode, bclk is also derived from sysclk via a programmable clock divide (bclkdiv). when the adclrc/gpio1 pin is configured as a gpio, a clock derived from sysclk can be output on this pin to provide clocking for other parts of the system. the frequency of this output clock is set by opclkdiv. a slow clock derived from sysclk is used to de-bounce the headphone detect function, and to set the timeout period for volume updates when zero-cross functions are used. this clock is enabled by toen and its frequency is set by toclksel. the class d outputs require a clock, and this is also derived from sysclk via a programmable divider (dclkdiv) as shown in figure 36. the clas s d switching clock should be set between 700khz and 800khz. the class d switching clock should not be disabled when the speaker outputs are active, as this would prevent the speaker outputs from functioning. the class d switching clock frequency should not be altered while the speaker outputs are active as this may generate an audible click. table 39 shows the clocking and sample rate controls for mclk input, bitclk output (in master mode), adcs, dacs, class d outputs and gpio cloc k output. refer to table 40 for example clocking configurations. register address bit label default description r4 (04h) clocking (1) 8:6 adcdiv [2:0] 000 adc sample rate divider (also determines adclrc in master mode) 000 = sysclk / (1.0 * 256) 001 = sysclk / (1.5 * 256) 010 = sysclk / (2 * 256) 011 = sysclk / (3 * 256) 100 = sysclk / (4 * 256) 101 = sysclk / (5.5 * 256) 110 = sysclk / (6 * 256) 111 = reserved 5:3 dacdiv [2:0] 000 dac sample rate divider (also determines daclrc in master mode) 000 = sysclk / (1.0 * 256) 001 = sysclk / (1.5 * 256) 010 = sysclk / (2 * 256) 011 = sysclk / (3 * 256) 100 = sysclk / (4 * 256) 101 = sysclk / (5.5 * 256) 110 = sysclk / (6 * 256) 111 = reserved 2:1 sysclkdiv [1:0] 00 sysclk pre-divider. clock source (mclk or pll output) will be divided by this value to generate sysclk. 00 = divide sysclk by 1 01 = reserved 10 = divide sysclk by 2 11 = reserved 0 clksel 0 sysclk selection 0 = sysclk derived from mclk 1 = sysclk derived from pll output
wm8960 production data w pd, october 2011, rev 4.1 58 register address bit label default description r8 (08h) clocking (2) 8:6 dclkdiv 111 class d switching clock divider. 000 = sysclk / 1.5 001 = sysclk / 2 010 = sysclk / 3 011 = sysclk / 4 100 = sysclk / 6 101 = sysclk / 8 110 = sysclk / 12 111 = sysclk / 16 3:0 bclkdiv[3:0] 0000 bclk frequency (master mode) 0000 = sysclk 0001 = sysclk / 1.5 0010 = sysclk / 2 0011 = sysclk / 3 0100 = sysclk / 4 0101 = sysclk / 5.5 0110 = sysclk / 6 0111 = sysclk / 8 1000 = sysclk / 11 1001 = sysclk / 12 1010 = sysclk / 16 1011 = sysclk / 22 1100 = sysclk / 24 1101 to 1111 = sysclk / 32 table 39 adc, dac and bclk control sysclk (=mclk or pll output) (mhz) adcdiv or dacdiv adc / dac sample rate (khz) 12.288 000 (=1) 48 001 (=1.5) 32 010 (=2) 24 011 (=3) 16 100 (=4) 12 101 (=5.5) (not used) 110 (=6) 8 111 reserved 11.2896 000 (=1) 44.1 001 (=1.5) (not used) 010 (=2) 22.05 011 (=3) (not used) 100 (=4) 11.025 101 (=5.5) 8.018 110 (=6) (not used) 111 reserved 2.048 000 (=1) 8 001 (=1.5) (not used) 010 (=2) (not used) 011 (=3) (not used) 100 (=4) (not used) 101 (=5.5) (not used) 110 (=6) (not used) 111 reserved table 40 adc and dac sample rates
production data wm8960 w pd, october 2011, rev 4.1 59 although the adc and dac can run at different sample rates, they share the same bit clock pin bclk. when operating in master mode, register bits bclkdiv[3:0] should be set to an appropriate value to ensure that there are sufficient bclk cycles to transfer the complete data word from the adcs and to the dacs. when operating in slave mode, the host device must provide sufficient bclk cycles to transfer complete data words to the adcs and dacs. table 41 shows the maximum word lengths supported for a given sysclk and bclkdiv, assuming that either the adcs or dacs are running at maximum rate (i.e. adcdiv[2:0]=000 or dacdiv[2:0]=000). sysclk (=mclk or pll output) (mhz) bclkdiv[3:0] bclk rate (master mode) (mhz) maximum word length (at maximum adc or dac sample rate) 12.288 0000 (=1) 12.288 32 0001 (=1.5) 8.192 32 0010 (=2) 6.144 32 0011 (=3) 4.096 32 0100 (=4) 3.072 32 0101 (=5.5) 2.2341818 20 0110 (=6) 2.048 20 0111 (=8) 1.536 16 1000 (=11) 1.117091 8 1001 (=12) 1.024 8 1010 (=16) 0.768 8 1011 (=22) 0.558545 n/a 1100 (=24) 0.512 n/a 1101 (=32) 0.384 n/a 1110 (=32) 0.384 n/a 1111 (=32) 0.384 n/a 11.2896 0000 (=1) 11.2896 32 0001 (=1.5) 7.5264 32 0010 (=2) 5.6448 32 0011 (=3) 3.7632 32 0100 (=4) 2.8224 32 0101 (=5.5) 2.052655 20 0110 (=6) 1.8816 20 0111 (=8) 1.4112 16 1000 (=11) 1.026327 8 1001 (=12) 0.9408 8 1010 (=16) 0.7056 8 1011 (=22) 0.513164 n/a 1100 (=24) 0.4704 n/a 1101 (=32) 0.3528 n/a 1110 (=32) 0.3528 n/a 1111 (=32) 0.3528 n/a table 41 bclk divider in master mode other sample rate control bits the alc, de-emphasis filter and 3d stereo enhance functions all need to be configured for the chosen sample rate when in use, as show in table 42. adc_alc_sr should be configured to match the chosen adc sample rate.
wm8960 production data w pd, october 2011, rev 4.1 60 deemph, 3duc and 3duc s hould be configured to match the chosen dac sample rate. register address bit label default description r27 (1bh) additional control (3) 2:0 adc_alc_sr [2:0] 000 alc sample rate 000 = 44.1k / 48k 001 = 32k 010 = 22.05k / 24k 011 = 16k 100 = 11.25k / 12k 101 = 8k 110 and 111 = reserved r5 (05h) adc and dac control (1) 2:1 deemph [1:0] 00 de-emphasis control 11 = 48khz sample rate 10 = 44.1khz sample rate 01 = 32khz sample rate 00 = no de-emphasis r16 (10h) 3d enhance 6 3duc 0 upper cut-off frequency 0 = high (recommended for fs>=32khz) 1 = low (recommended for fs<32khz) 5 3dlc 0 lower cut-off frequency 0 = low (recommended for fs>=32khz) 1 = high (recommended for fs<32khz) table 42 additional sample rate controls pll the integrated pll can be used to generate sysclk for the wm8960 or provide clocking for external devices via the gpio1 pin. the pll is enabled by the pllen register bit. register address bit label default description r26 (1ah) power management (2) 0 pllen 0 pll enable 0 = pll off 1 = pll on r52 (34h) pll (1) 5 sdm 0 enable integer mode 0 = integer mode 1 = fractional mode table 43 pllen control bit the pll frequency ratio r = f 2 /f 1 (see figure 36) can be set using the register bits pllk and plln: plln = int r pllk = int (2 24 (r-plln)) example: mclk=12mhz, required clock = 12.288mhz. r should be chosen to ensure 5 < plln < 13. there is a fixed divide by 4 in the pll and a selectable divide by n after the pll which should be set to divide by 2 to meet this requirement. enabling the divide by 2 sets the required f 2 = 4 x 2 x 12.288mhz = 98.304mhz. r = 98.304 / 12 = 8.192 plln = int r = 8 k = int ( 2 24 x (8.192 ? 8)) = 3221225 = 3126e9h
production data wm8960 w pd, october 2011, rev 4.1 61 register address bit label default description r52 (34h) pll n value 4 pllprescale 0 divide mclk by 2 before input to pll 0 = divide by 1 1 = divide by 2 3:0 plln 8h integer (n) part of pll input/output frequency ratio. use values greater than 5 and less than 13. r53 (35h) pll k value (1) 5:0 pllk [23:16] 31h fractional (k) part of pll1 input/output frequency ratio (treat as one 24-digit binary number). r54 (36h) pll k value (2) 8:0 pllk [15:8] 26h r55 (37h) pll k value (3) 8:0 pllk [7:0] e9h table 44 pll frequency ratio control the pll performs best when f 2 is between 90mhz and 100mhz. its stability peaks at n=8. some example settings are shown in table 45. mclk (mhz) (f1) desired output (sysclk) (mhz) f2 (mhz) prescale divide ( pllprescale ) postscale divide ( sysclkdiv [ 1:0 ]) fixed post-divide r n k 12 11.2896 90.3168 1 2 4 7.5264 7h 86c226h 12 12.288 98.304 1 2 4 8.192 8h 3126e8h 13 11.2896 90.3168 1 2 4 6.947446 6h f28bd4h 13 12.288 98.304 1 2 4 7.561846 7h 8fd525h 14.4 11.2896 90.3168 1 2 4 6.272 6h 45a1cah 14.4 12.288 98.304 1 2 4 6.826667 6h d3a06eh 19.2 11.2896 90.3168 2 2 4 9.408 9h 6872afh 19.2 12.288 98.304 2 2 4 10.24 ah 3d70a3h 19.68 11.2896 90.3168 2 2 4 9.178537 9h 2db492h 19.68 12.288 98.304 2 2 4 9.990243 9h fd809fh 19.8 11.2896 90.3168 2 2 4 9.122909 9h 1f76f7h 19.8 12.288 98.304 2 2 4 9.929697 9h ee009eh 24 11.2896 90.3168 2 2 4 7.5264 7h 86c226h 24 12.288 98.304 2 2 4 8.192 8h 3126e8h 26 11.2896 90.3168 2 2 4 6.947446 6h f28bd4h 26 12.288 98.304 2 2 4 7.561846 7h 8fd525h 27 11.2896 90.3168 2 2 4 6.690133 6h b0ac93h 27 12.288 98.304 2 2 4 7.281778 7h 482296h table 45 pll frequency examples
wm8960 production data w pd, october 2011, rev 4.1 62 device running in master mode with 24-bit data mclk input at 12.288mhz adc and dac running at fs=48khz bclk running at 64fs device running in slave mode with 24-bit data mclk input at 12.288mhz adc and dac running at fs=48khz bclk supplied from host at 64fs in this example device running in master mode with 24-bit data mclk input at 11.2896mhz adc running at fs=8.018khz dac running at fs=44.1khz bclk running at 64fs (relative to dac sample rate, as dac is operating at a higher sample rate than adc) device running in slave mode with 24-bit data mclk input at 11.2896mhz adc running at fs=8.018khz dac running at fs=44.1khz bclk supplied from host at 64fs in this example (relative to dac sample rate, as dac is operating at a higher sample rate than adc) device running in master mode with 24-bit data mclk input at 12mhz pll enabled and configured for sysclk=11.2896mhz adc running at fs=8.018khz dac running at fs=44.1khz bclk running at 64fs (relative to dac sample rate, as dac is operating at a higher sample rate than adc) class d clocks running at 705.6khz table 46 example clocking schemes
production data wm8960 w pd, october 2011, rev 4.1 63 control interface 2-wire serial control interface the wm8960 is controlled by writing to registers through a 2-wire serial control interface. a control word consists of 16 bits. the first 7 bits (b15 to b9) are address bits that select which control register is accessed. the remaining 9 bits (b8 to b0) are data bits, corresponding to the 9 bits in each control register. many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of each register in the wm8960). the device address is 0011010 ( 0x34h ). the wm8960 operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on sdin while sclk remains high. this indicates that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sdin (7-bit address + read/write bit, msb first). if the device address received matches the address of the wm8960 and the r/w bit is ?0?, indicating a write, then the wm8960 responds by pulling sdin low on the next clock pulse (ack). if the address is not recognised or the r/w bit is ?1?, the wm8960 returns to the idle condition and wait for a new start condition and valid address. once the wm8960 has acknowledged a correct address, the controller sends the first byte of control data (b15 to b8, i.e. the wm8960 register address plus the first bit of register data). the wm8960 then acknowledges the first data byte by pulling sd in low for one clock pulse. the controller then sends the second byte of control data (b7 to b0, i.e. the remaining 8 bits of register data), and the wm8960 acknowledges again by pulling sdin low. the transfer of data is complete when there is a low to high transition on sdin while sclk is high. after receiving a complete address and data sequence the wm8960 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sdin changes while sclk is high), the device jumps to the idle condition. sdin sclk register address and 1st register data bit device address (7 bits) rd / wr bit ack (low) control byte 1 (bits 15 to 8) control byte 2 (bits 7 to 0) remaining 8 bits of register data stop start ack (low) ack (low) figure 37 2-wire serial control interface power management the wm8960 has three control registers that allow users to select which functions are active. for minimum power consumption, unused functions should be disabled. to avoid any pop or click noise, it is important to enable or disable functions in the correct order (see applications information). vmidsel is the enable for the vmid reference, which defaults to disabled and can be enabled as a 2x50k ? potential divider or, for low power maintenance of vref when all other blocks are disabled, as a 2x250k ? potential divider.
wm8960 production data w pd, october 2011, rev 4.1 64 register address bit label default description r25 (19h) power management (1) 8:7 vmidsel 00 vmid divider enable and select 00 = vmid disabled (for off mode) 01 = 2 x 50k ? divider enabled (for playback / record) 10 = 2 x 250k ? divider enabled (for low- power standby) 11 = 2 x 5k ? divider enabled (for fast start- up) 6 vref 0 vref (necessary for all other functions) 0 = power down 1 = power up 5 ainl 0 analogue input pga and boost left 0 = power down 1 = power up (note: lmic must also be set to enable the pga) 4 ainr 0 analogue input pga and boost right 0 = power down 1 = power up (note: rmic must also be set to enable the pga) 3 adcl 0 adc left 0 = power down 1 = power up 2 adcr 0 adc right 0 = power down 1 = power up 1 micb 0 micbias 0 = power down 1 = power up 0 digenb 0 master clock disable 0 = master clock enabled 1 = master clock disabled
production data wm8960 w pd, october 2011, rev 4.1 65 register address bit label default description r26 (1ah) power management (2) 8 dacl 0 dac left 0 = power down 1 = power up 7 dacr 0 dac right 0 = power down 1 = power up 6 lout1 0 lout1 output buffer 0 = power down 1 = power up 5 rout1 0 rout1 output buffer 0 = power down 1 = power up 4 spkl 0 spk_lp/spk_ln output pga. 0 = power down 1 = power up (note: speaker output also requires spk_op_en[0] to be set) 3 spkr 0 spk_rp/spk_rn output pga 0 = power down 1 = power up (note: speaker output also requires spk_op_en[1] to be set) 1 out3 0 out3 output buffer 0 = power down 1 = power up 0 pll_en 0 pll enable 0 = power down 1 = power up r47 (2fh) power management (3) 5 lmic left input pga enable 0 = power down 1 = power up (note: pga also requires ainl to be set) 4 rmic right input pga enable 0 = power down 1 = power up (note: pga also requires ainr to be set) 3 lomix left output mixer enable 0 = power down 1 = power up 2 romix right output mixer enable 0 = power down 1 = power up table 47 power management
wm8960 production data w pd, october 2011, rev 4.1 66 stopping the master clock in order to minimise power consumed in the digital core of the wm8960, the master clock may be stopped in standby and off modes. if this cannot be done externally at the clock source, the digenb bit (r25, bit 0) can be set to stop the mclk signal from propagating into the device core. in standby mode, setting digenb will typically provide an additional power saving on dcvdd of 20ua. however, since setting digenb has no effect on the power consumption of other system components external to the wm8960, it is preferable to disable the master clock at its source wherever possible. mclk should not be stopped while the class d outputs are enabled, as this would prevent the outputs from functioning. register address bit label default description r25 (19h) additional control (1) 0 digenb 0 master clock disable 0 = master clock enabled 1 = master clock disabled table 48 enabling the master clock note: before digenb can be set, the control bits adcl, adcr, dacl and dacr must be set to zero and a waiting time of 1ms must be observed. any failure to follow this procedure may prevent dacs and adcs from re-starting correctly. saving power at higher supply voltage the avdd supply of the wm8960 can operate beteen 2.7v and 3.6v. by default, all analogue circuitry on the device is optimized to run at 3.3v. this set-up is also good for all other supply voltages down to 2.7v. at lower voltages, performance can be improved by increasing the bias current by setting vsel[1:0] = 01. if low power operation is preferred the bias current can be left at the default setting. this is controlled as shown below. register address bit label default description r23 (17h) additional control (1) 7:6 vsel [1:0] 11 analogue bias optimisation 00 = reserved 01 = increased bias current optimized for avdd=2.7v 1x = lowest bias current, optimized for avdd=3.3v table 49 bias optimisation
production data wm8960 w pd, october 2011, rev 4.1 67 register map register remarks bit[8] bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] default r0 (00h) left input volume ipvu linmute lizc 0_1001_0111 r1 (01h) right input volume ipvu rinmute rizc 0_1001_0111 r2 (02h) lout1 volume out1vu lo1zc 0_0000_0000 r3 (03h) rout1 volume out1vu ro1zc 0_0000_0000 r4 (04h) clocking (1) clksel 0_0000_0000 r5 (05h) adc & dac control (ctr1) 0 dacdiv2 0 dacmu adchpd 0_0000_1000 r6 (06h) adc & dac control (ctr2) 0 0 0 dacsmm dacmr dacslope 0 0_0000_0000 r7 (07h) audio interface alrswap bclkinv ms dlrswap lrp 0_0000_1010 r8 (08h) clocking (2) 00 1_1100_0000 r9 (09h) audio interface 0 0 alrcgpio wl8 loopback 0_0000_0000 r10 (0ah) left dac volume dacvu 0_1111_1111 r11 (0bh) right dac volume dacvu 0_1111_1111 r12 (0ch)reserved 0000000000_0 000_0000 r13 (0dh)reserved 0000000000_0 000_0000 r14 (0eh)reserved 0000000000_0 000_0000 r15 (0fh) reset not reset r16 (10h) 3d control 0 0 3duc 3dlc 3den 0_0000_0000 r17 (11h) alc1 0_0111_1011 r18 (12h) alc2 1 0 1_0000_0000 r19 (13h) alc3 alcmode 0_0011_0010 r20 (14h) noise gate 0 0 0 ngat 0_0000_0000 r21 (15h) left adc volume adcvu 0_1100_0011 r22 (16h) right adc volume adcvu 0_1100_0011 r23 (17h) additional control(1) tsden 0 dmonomix toclksel toen 1_1100_0000 r24 (18h) additional control(2) 0 0 hpswen hpswpol 0 tris lrcm 0 0 0_0000_0000 r25 (19h) pwr mgmt (1) vref ainl ainr adcl adcr micb digenb 0_0000_0000 r26 (1ah) pwr mgmt (2) dacl dacr lout1 rout1 spkl spkr 0 out3 pll_en 0_0000_0000 r27 (1bh) additional control (3) 0 0 vroi 0 0 out3cap 0_0000_0000 r28 (1ch) anti-pop 1 0 pobctrl 0 0 bufdcopen bufioen soft_st 0 hpstby 0_0000_0000 r29 (1dh) anti-pop 2 0 0 disop 0 0 0 0 0_0000_0000 r30 (1eh)reserved 0000000000_0 000_0000 r31 (1fh)reserved 0000000000_0 000_0000 r32 (20h) adcl signal path lmn1 lmp3 lmp2 lmic2b 0 0 0 1_0000_0000 r33 (21h) adcr signal path rmn1 rmp3 rmp2 rmic2b 0 0 0 1_0000_0000 r34 (22h) left out mix (1) ld2lo li2lo 0 0 0 0 0_0101_0000 r35 (23h)reserved 0010100000_0 101_0000 r36 (24h)reserved 0010100000_0 101_0000 r37 (25h) right out mix (2) rd2ro ri2ro 0 0 0 0 0_0101_0000 r38 (26h) mono out mix (1) 0 l2mo 0 0 0 0 0 0 0 0_0000_0000 r39 (27h) mono out mix (2) 0 r2mo 0 0 0 0 0 0 0 0_0000_0000 r40 (28h) lout2 volume spkvu spklzc 0_0000_0000 r41 (29h) rout2 volume spkvu spkrzc 0_0000_0000 r42 (2ah) monoout volume 0 0 moutvol 0 0 0 0 0 0 0_0100_0000 r43 (2bh) input boost mixer (1) 0 0 0 0_0000_0000 r44 (2ch) input boost mixer (2) 0 0 0 0_0000_0000 r45 (2dh) bypass (1) 0 lb2lo 0 0 0 0 0_0101_0000 r46 (2eh) bypass (2) 0 rb2ro 0 0 0 0 0_0101_0000 r47 (2fh) pwr mgmt (3) 0 0 0 lmic rmic lomix romix 0 0 0_0000_0000 r48 (30h) additional control (4) 0 gpiopol tsensen mbsel 0_0000_0010 r49 (31h) class d control (1) 0 1 1 0 1 1 1 0_0011_0111 r50 (32h)reserved 0010011010_0 100_1101 r51 (33h) class d control (3) 0 1 0 0_1000_0000 r52 (34h) pll n sdm pllrescale 0_0000_1000 r53 (35h) pll k 1 0 0_0011_0001 r54 (36h) pll k 2 0 0_0010_0110 r55 (37h) pll k 3 0 0_1110_1001 linvol[5:0] rinvol[5:0] lout1vol[6:0] rout1vol[6:0] adcdiv[2:0] dacdiv[2:0] sysclkdiv[1:0] adcpol[1:0] deemph[1:0] dacpol[1:0] wl[1:0] format[1:0] dclkdiv[2:0] bclkdiv[3:0] writing to this register resets all registers to their default state 3ddepth[3:0] daccomp[1:0] adccomp[1:0] ldacvol[7:0] rdacvol[7:0] dcy[3:0] atk[3:0] ngth[4:0] alcsel[1:0] maxgain[2:0] alcl[3:0] mingain[2:0] hld[3:0] vmidsel[1:0] adc_alc_sr[2:0] ladcvol[7:0] radcvol[7:0] vsel[1:0] datsel[1:0] ri2rovol[2:0] spklvol[6:0] lmicboost[1:0] rmicboost[1:0] li2lovol[2:0] rb2rovol[2:0] gpiosel[2:0] hpsel[1:0] spkrvol[6:0] lin3boost[2:0] lin2boost[2:0] rin3boost[2:0] rin2boost[2:0] dres[1:0] pllk[23:16] pllk[15:8] pllk[7:0] dcgain[2:0] acgain[2:0] opclkdiv[2:0] plln[3:0] spk_op_en[1:0] lb2lovol[2:0]
wm8960 production data w pd, october 2011, rev 4.1 68 register bits by address register address bit label default description refer to r0 (00h) left input volume 8 ipvu n/a input pga volume update writing a 1 to this bit will cause left and right input pga volumes to be updated (linvol and rinvol) input signal path 7 linmute 1 left input pga analogue mute 1 = enable mute 0 = disable mute note: ipvu must be set to un-mute. input signal path 6 lizc 0 left input pga zero cross detector 1 = change gain on zero cross only 0 = change gain immediately input signal path 5:0 linvol[5:0] 010111 left input pga volume control 111111 = +30db 111110 = +29.25db . . 0.75db steps down to 000000 = -17.25db input signal path r1 (01h) right input volume 8 ipvu n/a input pga volume update writing a 1 to this bit will cause left and right input pga volumes to be updated (linvol and rinvol) input signal path 7 rinmute 1 right input pga analogue mute 1 = enable mute 0 = disable mute note: ipvu must be set to un-mute. input signal path 6 rizc 0 right input pga zero cross detector 1 = change gain on zero cross only 0 = change gain immediately input signal path 5:0 rinvol[5:0] 010111 right input pga volume control 111111 = +30db 111110 = +29.25db . . 0.75db steps down to 000000 = -17.25db input signal path r2 (02h) lout1 volume 8 out1vu n/a headphone output pga volume update writing a 1 to this bit will cause left and right headphone output volumes to be updated (lout1vol and rout1vol) analogue outputs 7 lo1zc 0 left headphone output zero cross enable 0 = change gain immediately 1 = change gain on zero cross only analogue outputs 6:0 lout1vol[6:0] 0000000 lout1 volume 1111111 = +6db ? 1db steps down to 0110000 = -73db 0101111 to 0000000 = analogue mute analogue outputs r3 (03h) rout1 volume 8 out1vu n/a headphone output pga volume update writing a 1 to this bit will cause left and right headphone output volumes to be updated (lout1vol and rout1vol) analogue outputs 7 ro1zc 0 right headphone output zero cross enable 0 = change gain immediately 1 = change gain on zero cross only analogue outputs
production data wm8960 w pd, october 2011, rev 4.1 69 register address bit label default description refer to 6:0 rout1vol[6:0] 0000000 rout1 volume 1111111 = +6db ? 1db steps down to 0110000 = -73db 0101111 to 0000000 = analogue mute analogue outputs r4 (04h) clocking (1) 8:6 adcdiv[2:0] 000 adc sample rate divider (also determines adclrc in master mode) 000 = sysclk / (1.0 * 256) 001 = sysclk / (1.5 * 256) 010 = sysclk / (2 * 256) 011 = sysclk / (3 * 256) 100 = sysclk / (4 * 256) 101 = sysclk / (5.5 * 256) 110 = sysclk / (6 * 256) 111 = reserved clocking and sample rates 5:3 dacdiv[2:0] 000 dac sample rate divider (also determines daclrc in master mode) 000 = sysclk / (1.0 * 256) 001 = sysclk / (1.5 * 256) 010 = sysclk / (2 * 256) 011 = sysclk / (3 * 256) 100 = sysclk / (4 * 256) 101 = sysclk / (5.5 * 256) 110 = sysclk / (6 * 256) 111 = reserved clocking and sample rates 2:1 sysclkdiv[1:0] 00 sysclk pre-divider. clock source (mclk or pll output) will be divided by this value to generate sysclk. 00 = divide sysclk by 1 01 = reserved 10 = divide sysclk by 2 11 = reserved clocking and sample rates 0 clksel 0 sysclk selection 0 = sysclk derived from mclk 1 = sysclk derived from pll output clocking and sample rates r5 (05h) adc and dac control (1) 8 0 reserved 7 dacdiv2 0 dac 6db attenuate enable 0 = disabled (0db) 1 = -6db enabled output signal path 6:5 adcpol[1:0] 00 adc polarity control: 00 = polarity not inverted 01 = adc l inverted 10 = adc r inverted 11 = adc l and r inverted analogue to digital converter 4 0 reserved 3 dacmu 1 dac digital soft mute 1 = mute 0 = no mute (signal active) output signal path 2:1 deemph[1:0] 00 de-emphasis control 11 = 48khz sample rate 10 = 44.1khz sample rate 01 = 32khz sample rate 00 = no de-emphasis output signal path
wm8960 production data w pd, october 2011, rev 4.1 70 register address bit label default description refer to 0 adchpd 0 adc high pass filter disable 0 = enable high pass filter on left and right channels 1 = disable high pass filter on left and right channels analogue to digital converter r6 (06h) adc and dac control (2) 8:7 00 reserved 6:5 dacpol[1:0] 00 dac polarity control: 00 = polarity not inverted 01 = dac l inverted 10 = dac r inverted 11 = dac l and r inverted output signal path 4 0 reserved 3 dacsmm 0 dac soft mute mode 0 = disabling soft-mute (dacmu=0) will cause the volume to change immediately to the ldacvol / rdacvol settings 1 = disabling soft-mute (dacmu=0) will cause the volume to ramp up gradually to the ldacvol / rdacvol settings output signal path 2 dacmr 0 dac soft mute ramp rate 0 = fast ramp (24khz at fs=48k, providing maximum delay of 10.7ms) 1 = slow ramp (1.5khz at fs=48k, providing maximum delay of 171ms) output signal path 1 dacslope 0 selects dac filter characteristics 0 = normal mode 1 = sloping stopband output signal path 0 0 reserved r7 (07h) audio interface 8 alrswap 0 left/right adc channel swap 1 = swap left and right adc data in audio interface 0 = output left and right data as normal audio interface control 7 bclkinv 0 bclk invert bit (for master and slave modes) 0 = bclk not inverted 1 = bclk inverted audio interface control 6 ms 0 master / slave mode control 0 = enable slave mode 1 = enable master mode audio interface control 5 dlrswap 0 left/right dac channel swap 0 = output left and right data as normal 1 = swap left and right dac data in audio interface audio interface control 4 lrp 0 right, left and i 2 s modes ? lrclk polarity 0 = normal lrclk polarity 1 = invert lrclk polarity audio interface control dsp mode ? mode a/b select 0 = msb is available on 2nd bclk rising edge after lrc rising edge (mode a) 1 = msb is available on 1st bclk rising edge after lrc rising edge (mode b) 3:2 wl[1:0] 10 audio data word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits (see note) audio interface control
production data wm8960 w pd, october 2011, rev 4.1 71 register address bit label default description refer to 1:0 format[1:0] 10 00 = right justified 01 = left justified 10 = i 2 s format 11 = dsp mode audio interface control r8 (08h) clocking (2) 8:6 dclkdiv[2:0] 111 class d switching clock divider. 000 = sysclk / 1.5 (not recommended) 001 = sysclk / 2 010 = sysclk / 3 011 = sysclk / 4 100 = sysclk / 6 101 = sysclk / 8 110 = sysclk / 12 111 = sysclk / 16 class d speaker outputs; clocking and sample rates 5:4 00 reserved 3:0 bclkdiv[3:0] 0000 bclk frequency (master mode) 0000 = sysclk 0001 = sysclk / 1.5 0010 = sysclk / 2 0011 = sysclk / 3 0100 = sysclk / 4 0101 = sysclk / 5.5 0110 = sysclk / 6 0111 = sysclk / 8 1000 = sysclk / 11 1001 = sysclk / 12 1010 = sysclk / 16 1011 = sysclk / 22 1100 = sysclk / 24 1101 to 1111 = sysclk / 32 clocking and sample rates r9 (09h) audio interface 8:7 00 reserved 6 alrcgpio 0 adclrc/gpio1 pin function select 0 = adclrc frame clock for adc 1 = gpio pin general purpose input / output; digital audio interface 5 wl8 0 8-bit word length select (used with companding) 0 = off 1 = device operates in 8-bit mode. audio interface control 4:3 daccomp[1:0] 00 dac companding 00 = off 01 = reserved 10 = -law 11 = a-law audio interface control 2:1 adccomp[1:0] 00 adc companding 00 = off 01 = reserved 10 = -law 11 = a-law audio interface control 0 loopback 0 digital loopback function 0 = no loopback. 1 = loopback enabled, adc data output is fed directly into dac data input. audio interface control
wm8960 production data w pd, october 2011, rev 4.1 72 register address bit label default description refer to r10 (0ah) left dac volume 8 dacvu n/a dac volume update writing a 1 to this bit will cause left and right dac volumes to be updated (ldacvol and rdacvol) output signal path 7:0 ldacvol[7:0] 11111111 left dac digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db output signal path r11 (0bh) right dac volume 8 dacvu n/a dac volume update writing a 1 to this bit will cause left and right dac volumes to be updated (ldacvol and rdacvol) output signal path 7:0 rdacvol[7:0] 11111111 right dac digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db output signal path r12 (0ch) 8:0 000000000 reserved r13 (0dh) 8:0 000000000 reserved r14 (0eh) 8:0 000000000 reserved r15 (0fh) reset 8:0 reset n/a writing to this register resets all registers to their default state. r16 {10h) 3d control 8 0 reserved 7 0 reserved 6 3duc 0 3d enhance filter upper cut-off frequency 0 = high (recommended for fs>=32khz) 1 = low (recommended for fs<32khz) output signal path 5 3dlc 0 3d enhance filter lower cut-off frequency 0 = low (recommended for fs>=32khz) 1 = high (recommended for fs<32khz) output signal path 4:1 3ddepth[3:0] 0000 3d stereo depth 0000 = 0% (minimum 3d effect) 0001 = 6.67% .... 1110 = 93.3% 1111 = 100% (maximum 3d effect) output signal path 0 3den 0 3d stereo enhancement enable 0 = disabled 1 = enabled output signal path r17 (11h) alc (1) 8:7 alcsel[1:0] 00 alc function select 00 = alc off (pga gain set by register) 01 = right channel only 10 = left channel only 11 = stereo (pga registers unused) note: ensure that linvol and rinvol settings (reg. 0 and 1) are the same before entering this mode. automatic level control
production data wm8960 w pd, october 2011, rev 4.1 73 register address bit label default description refer to 6:4 maxgain[2:0] 0000 set maximum gain of pga (during alc operation) 111 : +30db 110 : +24db ?.(-6db steps) 001 : -6db 000 : -12db automatic level control 3:0 alcl[3:0] 1011 alc target (sets signal level at adc input) 0000 = -22.5db fs 0001 = -21.0db fs ? (1.5db steps) 1101 = -3.0db fs 1110 = -1.5db fs 1111 = -1.5db fs automatic level control r18 (12h) alc (2) 8 1 reserved 7 0 reserved 6:4 mingain[2:0] 000 set minimum gain of pga (during alc operation) 000 = -17.25db 001 = -11.25db 010 = -5.25db 011 = +0.75db 100 = +6.75db 101 = +12.75db 110 = +18.75db 111 = +24.75db automatic level control 3:0 hld[3:0] 0000 alc hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ? (time doubles with every step) 1111 = 43.691s automatic level control r19 (13h) alc (3) 8 alcmode 0 determines the alc mode of operation: 0 = alc mode 1 = limiter mode automatic level control 7:4 dcy[3:0] 0011 alc decay (gain ramp-up) time 0000 = 24ms 0001 = 48ms 0010 = 96ms ? (time doubles with every step) 1010 or higher = 24.58s automatic level control 3:0 atk[3:0] 0010 alc attack (gain ramp-down) time 0000 = 6ms 0001 = 12ms 0010 = 24ms ? (time doubles with every step) 1010 or higher = 6.14s automatic level control r20 (14h) noise gate 8 0 reserved 7:3 ngth[4:0] 00000 noise gate threshold 00000 -76.5dbfs 00001 -75dbfs ? 1.5 db steps 11110 -31.5dbfs 11111 -30dbfs automatic level control
wm8960 production data w pd, october 2011, rev 4.1 74 register address bit label default description refer to 2:1 00 reserved 0 ngat 0 noise gate function enable 0 = disable 1 = enable automatic level control r21 (15h) left adc volume 8 adcvu n/a adc volume update writing a 1 to this bit will cause left and right adc volumes to be updated (ladcvol and radcvol) analogue to digital converter 7:0 ladcvol[7:0] 11000011 left adc digital volume control 0000 0000 = digital mute 0000 0001 = -97db 0000 0010 = -96.5db ... 0.5db steps up to 1111 1111 = +30db analogue to digital converter r22 (16h) right adc volume 8 adcvu n/a adc volume update writing a 1 to this bit will cause left and right adc volumes to be updated (ladcvol and radcvol) analogue to digital converter 7:0 radcvol[7:0] 11000011 right adc digital volume control 0000 0000 = digital mute 0000 0001 = -97db 0000 0010 = -96.5db ... 0.5db steps up to 1111 1111 = +30db analogue to digital converter r23 (17h) additional control (1) 8 tsden 1 thermal shutdown enable 0 = thermal shutdown disabled 1 = thermal shutdown enabled (tsensen must be enabled for this function to work) thermal shutdown 7:6 vsel[1:0] 11 analogue bias optimisation 00 = reserved 01 = increased bias current optimized for avdd=2.7v 1x = lowest bias current, optimized for avdd=3.3v power management 5 0 reserved 4 dmonomix 0 dac mono mix 0 = stereo 1 = mono (mono mix output on enabled dacs) output signal path 3:2 datsel[1:0] 00 adc data output select 00: left data = left adc; right data =right adc 01: left data = left adc; right data = left adc 10: left data = right adc; right data =right adc 11: left data = right adc; right data = left adc analogue to digital converter 1 toclksel 0 slow clock select (used for volume update timeouts and for jack detect debounce) 0 = sysclk / 2 21 (slower response) 1 = sysclk / 2 19 (faster response) volume updates; headphone jack detect 0 toen 0 enables slow clock for volume update timeout and jack detect debounce 0 = slow clock disabled 1 = slow clock enabled volume updates; headphone jack detect r24 (18h) 8:7 00 reserved
production data wm8960 w pd, october 2011, rev 4.1 75 register address bit label default description refer to additional control (2) 6 hpswen 0 headphone switch enable 0 = headphone switch disabled 1 = headphone switch enabled headphone jack detect 5 hpswpol 0 headphone switch polarity 0 = hpdetect high = headphone 1 = hpdetect high = speaker headphone jack detect 4 reserved 3 tris 0 tristates adcdat and switches adclrc, daclrc and bclk to inputs. 0 = adcdat is an output; adclrc, daclrc and bclk are inputs (slave mode) or outputs (master mode) 1 = adcdat is tristated; daclrc and bclk are inputs; adclrc is an input (when not configured as a gpio) audio interface control 2 lrcm 0 selects disable mode for adclrc and daclrc (master mode) 0 = adclrc disabled when adc (left and right) disabled; daclrc disabled when dac (left and right) disabled. 1 = adclrc and daclrc disabled only when adc (left and right) and dac (left and right) are disabled. audio interface control 1:0 0 reserved r25 (19h) power mgmt (1) 8:7 vmidsel[1:0] 00 vmid divider enable and select 00 = vmid disabled (for off mode) 01 = 2 x 50k ? divider enabled (for playback / record) 10 = 2 x 250k ? divider enabled (for low-power standby) 11 = 2 x 5k ? divider enabled (for fast start-up) power management 6 vref 0 vref (necessary for all other functions) 0 = power down 1 = power up power management 5 ainl 0 analogue in pga left 0 = power down 1 = power up power management 4 ainr 0 analogue in pga right 0 = power down 1 = power up power management 3 adcl 0 adc left 0 = power down 1 = power up power management 2 adcr 0 adc right 0 = power down 1 = power up power management 1 micb 0 micbias 0 = power down 1 = power up power management 0 digenb 0 master clock disable 0 = master clock enabled 1 = master clock disabled power management r26 (1ah) power mgmt (2) 8 dacl 0 dac left 0 = power down 1 = power up power management
wm8960 production data w pd, october 2011, rev 4.1 76 register address bit label default description refer to 7 dacr 0 dac right 0 = power down 1 = power up power management 6 lout1 0 lout1 output buffer 0 = power down 1 = power up power management 5 rout1 0 rout1 output buffer 0 = power down 1 = power up power management 4 spkl 0 spk_lp/spk_ln output buffers 0 = power down 1 = power up power management 3 spkr 0 spk_rp/spk_rn output buffers 0 = power down 1 = power up power management 2 0 reserved 1 out3 0 out3 output buffer 0 = power down 1 = power up power management 0 pll_en 0 pll enable 0 = power down 1 = power up power management r27 (1bh) additional control (3) 8:7 00 reserved 6 vroi 0 vref to analogue output resistance (disabled outputs) 0 = 500 ? vmid to output 1 = 20k ? vmid to output enabling the outputs 5 0 reserved 4 0 reserved 3 out3cap 0 capless mode headphone switch enable 0 = out3 unaffected by jack detect events 1 = out3 enabled and disabled together with hp_l and hp_r in response to jack detect events headphone jack detect 2:0 adc_alc_sr 000 alc sample rate 000 = 44.1k / 48k 001 = 32k 010 = 22.05k / 24k 011 = 16k 100 = 11.25k / 12k 101 = 8k 110 and 111 = reserved automatic level control r28 (1ch) anti-pop 1 8 0 reserved 7 pobctrl 0 selects the bias current source for output amplifiers and vmid buffer 0 = vmid / r bias 1 = vgs / r bias 6:5 00 reserved 4 bufdcopen 0 enables the vgs / r current generator 0 = disabled 1 = enabled
production data wm8960 w pd, october 2011, rev 4.1 77 register address bit label default description refer to 3 bufioen 0 enables the vgs / r current generator and the analogue input and output bias 0 = disabled 1 = enabled 2 soft_st 0 enables vmid soft start 0 = disabled 1 = enabled 1 0 reserved 0 hpstby 0 headphone amplifier standby 0 = standby mode disabled (normal operation) 1 = standby mode enabled r29 (1dh) anti-pop 2 8:7 00 reserved 6 disop 0 discharges the dc-blocking headphone capacitors on hp_l and hp_r 0 = disabled 1 = enabled 5:4 dres[1:0] 00 dres determines the value of the resistors used to discharge the dc-blocking headphone capacitors when disop=1 dres[1:0] resistance (ohms) 0 0 400 0 1 200 1 0 600 1 1 150 3:0 0000 reserved r30 (1eh) 8:0 000000000 reserved r31 (1fh) 8:0 000000000 reserved r32 (20h) adcl signal path 8 lmn1 1 connect linput1 to inverting input of left input pga 0 = linput1 not connected to pga 1 = linput1 connected to pga input signal path 7 lmp3 0 connect linput3 to non-inverting input of left input pga 0 = linput3 not connected to pga 1 = linput3 connected to pga (constant input impedance) input signal path 6 lmp2 0 connect linput2 to non-inverting input of left input pga 0 = linput2 not connected to pga 1 = linput2 connected to pga (constant input impedance) input signal path 5:4 lmicboost[1:0] 00 left channel input pga boost gain 00 = +0db 01 = +13db 10 = +20db 11 = +29db input signal path 3 lmic2b 0 connect left input pga to left input boost mixer 0 = not connected 1 = connected input signal path 2:0 000 reserved r33 (21h) adcr signal path 8 rmn1 1 connect rinput1 to inverting input of right input pga 0 = rinput1 not connected to pga 1 = rinput1 connected to pga input signal path
wm8960 production data w pd, october 2011, rev 4.1 78 register address bit label default description refer to 7 rmp3 0 connect rinput3 to non-inverting input of right input pga 0 = rinput3 not connected to pga 1 = rinput3 connected to pga (constant input impedance) input signal path 6 rmp2 0 connect rinput2 to non-inverting input of right input pga 0 = rinput2 not connected to pga 1 = rinput2 connected to pga (constant input impedance) input signal path 5:4 rmicboost[1:0] 00 right channel input pga boost gain 00 = +0db 01 = +13db 10 = +20db 11 = +29db input signal path 3 rmic2b 0 connect right input pga to right input boost mixer 0 = not connected 1 = connected input signal path 2:0 000 reserved r34 (22h) left out mix 8 ld2lo 0 left dac to left output mixer 0 = disable (mute) 1 = enable path output signal path 7 li2lo 0 linput3 to left output mixer 0 = disable (mute) 1 = enable path output signal path 6:4 li2lovol[2:0] 101 linput3 to left output mixer volume 000 = 0db ...(3db steps) 111 = -21db output signal path 3:0 0000 reserved r35 (23h) 8:0 001010000 reserved r36 (24h) 8:0 001010000 reserved r37 (25h) right out mix 8 rd2ro 0 right dac to right output mixer 0 = disable (mute) 1 = enable path output signal path 7 ri2ro 0 rinput3 to right output mixer 0 = disable (mute) 1 = enable path output signal path 6:4 ri2rovol[2:0] 101 rinput3 to right output mixer volume 000 = 0db ...(3db steps) 111 = -21db output signal path 3:0 0000 reserved r38 (26h) mono out mix (1) 8 0 reserved 7 l2mo 0 left output mixer to mono output mixer control 0 = left channel mix disabled 1 = left channel mix enabled output signal path 6:0 0000000 reserved r39 (27h) mono out mix (2) 8 0 reserved 7 r2mo 0 right output mixer to mono output mixer control 0 = right channel mix disabled 1 = right channel mix enabled output signal path 6:0 0000000 reserved
production data wm8960 w pd, october 2011, rev 4.1 79 register address bit label default description refer to r40 (28h) left speaker volume 8 spkvu n/a speaker volume update writing a 1 to this bit will cause left and right speaker volumes to be updated (spklvol and spkrvol) analogue outputs 7 spklzc 0 left speaker zero cross enable 1 = change gain on zero cross only 0 = change gain immediately analogue outputs 6:0 spklvol[6:0] 0000000 spk_lp/spk_ln volume 1111111 = +6db ? 1db steps down to 0110000 = -73db 0101111 to 0000000 = analogue mute analogue outputs r41 (29h) right speaker volume 8 spkvu n/a speaker volume update writing a 1 to this bit will cause left and right speaker volumes to be updated (spklvol and spkrvol) analogue outputs 7 spkrzc 0 right speaker zero cross enable 1 = change gain on zero cross only 0 = change gain immediately analogue outputs 6:0 spkrvol[6:0] 0000000 spk_rp/spk_rn volume 1111111 = +6db ? 1db steps down to 0110000 = -73db 0101111 to 0000000 = analogue mute analogue outputs r42 (2ah) out3 volume 8:7 00 reserved 6 moutvol 1 mono output mixer volume control 0 = 0db 1 = -6db output signal path 5:0 000000 reserved r43 (2bh) left input boost mixer 8:7 00 reserved 6:4 lin3boost[2:0] 000 linput3 to boost mixer gain 000 = mute 001 = -12db ...3db steps up to 111 = +6db input signal path 3:1 lin2boost[2:0] 000 linput2 to boost mixer gain 000 = mute 001 = -12db ...3db steps up to 111 = +6db input signal path 0 0 reserved r44 (2ch) right input boost mixer 8:7 00 reserved 6:4 rin3boost[2:0] 000 rinput3 to boost mixer gain 000 = mute 001 = -12db ...3db steps up to 111 = +6db input signal path 3:1 rin2boost[2:0] 000 rinput2 to boost mixer gain 000 = mute 001 = -12db ...3db steps up to 111 = +6db input signal path 0 0 reserved r45 (2dh) 8 0 reserved
wm8960 production data w pd, october 2011, rev 4.1 80 register address bit label default description refer to left bypass 7 lb2lo 0 left input boost mixer to left output mixer 0 = disable (mute) 1 = enable path output signal path 6:4 lb2lovol[2:0] 101 left input boost mixer to left output mixer volume 000 = 0db ...(3db steps) 111 = -21db output signal path 3:0 0000 reserved r46 (2eh) right bypass 8 0 reserved 7 rb2ro 0 right input boost mixer to right output mixer 0 = disable (mute) 1 = enable path output signal path 6:4 rb2rovol[2:0] 101 right input boost mixer to right output mixer volume 000 = 0db ...(3db steps) 111 = -21db output signal path 3:0 0000 reserved r47 (2fh) power mgmt (3) 8:6 000 reserved 5 lmic 0 left channel input pga enable 0 = pga disabled 1 = pga enabled (if ainl = 1) input signal path 4 rmic 0 right channel input pga enable 0 = pga disabled 1 = pga enabled (if ainr = 1) input signal path 3 lomix 0 left output mixer enable control 0 = disabled 1 = enabled output signal path 2 romix 0 right output mixer enable control 0 = disabled 1 = enabled output signal path 1:0 00 reserved r48 (30h) additional control (4) 8 0 reserved 7 gpiopol 0 gpio polarity invert 0 = non inverted 1 = inverted general purpose input / output 6:4 gpiosel[2:0] 000 adclrc/gpio1 gpio function select: 000 = jack detect input 001 = reserved 010 = temperature ok 011 = debounced jack detect output 100 = sysclk output 101 = pll lock 110 = logic 0 111 = logic 1 general purpose input / output 3:2 hpsel[1:0] 00 headphone switch input select 0x = gpio1 used for jack detect input (requires adclrc pin to be configured as a gpio) 10 = jd2 used for jack detect input 11 = jd3 used for jack detect input headphone jack detect 1 tsensen 1 temperature sensor enable 0 = temperature sensor disabled 1 = temperature sensor enabled thermal shutdown
production data wm8960 w pd, october 2011, rev 4.1 81 register address bit label default description refer to 0 mbsel 0 microphone bias voltage control 0 = 0.9 * avdd 1 = 0.65 * avdd input signal path r49 (31h) class d control (1) 8 0 reserved 7:6 spk_op_en[1:0] 00 enable class d speaker outputs 00 = off 01 = left speaker only 10 = right speaker only 11 = left and right speakers enabled enabling the outputs 5:0 110111 reserved r50 (32h) 8:0 001001101 reserved r51 (33h) class d control (2) 8:6 010 reserved 5:3 dcgain[2:0] 000 dc speaker b oost (boosts speaker dc output level by up to 1.8 x on left and right channels) 000 = 1.00x boost (+0db) 001 = 1.27x boost (+2.1db) 010 = 1.40x boost (+2.9db) 011 = 1.52x boost (+3.6db) 100 = 1.67x boost (+4.5db) 101 = 1.8x boost (+5.1db) 110 to 111 = reserved analogue outputs 2:0 acgain[2:0] 000 ac speaker boost (boosts speaker ac output signal by up to 1.8 x on left and right channels) 000 = 1.00x boost (+0db) 001 = 1.27x boost (+2.1db) 010 = 1.40x boost (+2.9db) 011 = 1.52x boost (+3.6db) 100 = 1.67x boost (+4.5db) 101 = 1.8x boost (+5.1db) 110 to 111 = reserved analogue outputs r52 (34h) pll (1) 8:6 opclkdiv[2:0] 000 sysclk output to gpio clock division ratio 000 = sysclk 001 = sysclk / 2 010 = sysclk / 3 011 = sysclk / 4 100 = sysclk / 5.5 101 = sysclk / 6 general purpose input / output 5 sdm 0 enable integer mode 0 = integer mode 1 = fractional mode clocking and sample rates 4 pllprescale 0 divide mclk by 2 before input to pll 0 = divide by 1 1 = divide by 2 clocking and sample rates 3:0 plln[3:0] 1000 integer (n) part of pll input/output frequency ratio. use values greater than 5 and less than 13. clocking and sample rates r53 (35h) pll (2) 8 0 reserved 7:0 pllk[23:16] 00110001 fractional (k) part of pll1 input/output frequency ratio (treat as one 24-digit binary number). clocking and sample rates r54 (36h) pll (3) 8 0 reserved 7:0 pllk[15:8] 00100110 fractional (k) part of pll1 input/output frequency ratio (treat as one 24-digit binary number). clocking and sample rates
wm8960 production data w pd, october 2011, rev 4.1 82 register address bit label default description refer to r55 (37h) pll (4) 8 0 reserved 7:0 pllk[7:0] 11101001 fractional (k) part of pll1 input/output frequency ratio (treat as one 24-digit binary number). clocking and sample rates digital filter characteristics parameter test conditions min typ max unit adc filter passband +/- 0.05db 0 0.454 fs -6db 0.5fs passband ripple +/- 0.05 db stopband 0.546s stopband attenuation f > 0.546 fs -60 db dac normal filter passband +/- 0.03db 0 0.454 fs -6db 0.5 fs passband ripple 0.454 fs +/- 0.03 db stopband 0.546 fs stopband attenuation f > 0.546 fs -50 db dac sloping stopband filter passband +/- 0.03db 0 0.25 fs +/- 1db 0.25 fs 0.454 fs -6db 0.5 fs passband ripple 0.25 fs +/- 0.03 db stopband 1 0.546 fs 0.7 fs stopband 1 attenuation f > 0.546 fs -60 db stopband 2 0.7 fs 1.4 fs stopband 2 attenuation f > 0.7 fs -85 db stopband 3 1.4 fs stopband 3 attenuation f > 1.4 fs -55 db dac filters adc filters mode group delay mode group delay normal 18 / fs normal 18 / fs sloping stopband 18 / fs
production data wm8960 w pd, october 2011, rev 4.1 83 adc filter responses -150 -130 -110 -90 -70 -50 -30 -10 10 0 0.1 0.2 0.3 0.4 0.51 0.61 0.71 0.81 0.91 1.01 1.11 1.21 1.31 1.42 1.52 1.62 1.72 1.82 1.92 2.02 2.12 2.22 2.33 2.43 2.53 2.63 2.73 2.83 2.93 3.03 3.13 3.24 3.34 3.44 3.54 3.64 3.74 3.84 3.94 frequency (fs) magnitude (db) magnitude (db): passband ripple -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 0.00 0.25 frequency figure 38 adc digital filter frequency response figure 39 adc digital filter ripple dac filter responses dac stopband attenuation the dac digital filter type is selected by the dacslope register bit as shown in table 50. register address bit label default description r6 (06h) adc and dac control (2) 1 dacslope 0 selects dac filter characteristics 0 = normal mode 1 = sloping stopband mode table 50 dac filter selection magnitude(db) -150 -130 -110 -90 -70 -50 -30 -10 10 0 0.5 1 1.5 2 2.5 3 frequency (fs) magnitude(db) -0.005 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (fs) figure 40 dac digital filter frequency response (normal mode) figure 41 dac digital filter ripple (normal mode)
wm8960 production data w pd, october 2011, rev 4.1 84 magnitude(db) -150 -130 -110 -90 -70 -50 -30 -10 10 0 0.5 1 1.5 2 2.5 3 frequency (fs) magnitude(db) -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (fs) figure 42 dac digital filter frequency response (sloping stopband mode) figure 43 dac digital filter ripple (sloping stopband mode)
production data wm8960 w pd, october 2011, rev 4.1 85 de-emphasis filter responses magnitude(db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 5000 10000 15000 20000 frequency (hz) magnitude(db) -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 frequency (hz) figure 44 de-emphasis digital filter response (32khz) figure 45 de-emphasis error (32khz) magnitude(db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 5000 10000 15000 20000 25000 frequency (hz) magnitude(db) -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 5000 10000 15000 20000 25000 frequency (hz) figure 46 de-emphasis digital filter response (44.1khz) figure 47 de-emphasis error (44.1khz) magnitude(db) -12 -10 -8 -6 -4 -2 0 0 5000 10000 15000 20000 25000 30000 frequency (hz) magnitude(db) -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0 5000 10000 15000 20000 25000 30000 frequency (hz) figure 48 de-emphasis digital filter response (48khz) figure 49 de-emphasis error (48khz)
wm8960 production data w pd, october 2011, rev 4.1 86 applications information recommended external components speaker selection for filterless operation, it is important to select a speaker with appropriate internal inductance. the internal inductance and the speaker's load resistance create a low-pass filter with a cut-off frequency of: f c = r l / 2 ? l e.g. for an 8 ? speaker and required cut-off frequency of 20khz, the speaker should be chosen to have an inductance of: l = r l / 2 ? f c = 8 ? / 2 ? * 20khz = 64 ? h 8 ? speakers typically have an inductance in the range 20 ? h to 100 ? h. care should be taken to ensure that the cut-off frequency of the speaker's inter nal filtering is low enough to prevent speaker damage. the class d outputs of the wm8960 operate at much higher frequencies than is recommended for most speakers, and the cut-off frequency of the filter should be low enough to protect the speaker.
production data wm8960 w pd, october 2011, rev 4.1 87 figure 50 speaker equivalent circuit pcb layout considerations the efficiency of the speaker drivers is affected by the series resistance between the wm8960 and the speaker (e.g. inductor esr) as shown in figur e 51. this resistance should be as low as possible to maximise efficiency. figure 51 speaker connection losses the distance between the wm8960 and the speakers should be kept to a minimum to reduce series resistance, and also to reduce emi. further reductions in emi can be achieved by additional passive filtering and/or shielding as shown in figure 52. when additional passive filtering is used, low esr components should be chosen to minimise series resistance between the wm8960 and the speaker, maximising efficiency. lc passive filtering will usually be effective at reducing emi at frequencies up to around 30mhz. to reduce emissions at higher frequencies, ferrite beads pl aced as close to the device as possible will be more effective. note: refer to the application note wan_0118 on ?guidelines on how to use qfn packages and create associated pcb footprints?
wm8960 production data w pd, october 2011, rev 4.1 88 figure 52 emi reduction techniques
production data wm8960 w pd, october 2011, rev 4.1 89 package dimensions dm101.a fl: 32 pin qfn plastic package 5 x 5 x 0.9 mm body, 0.50 mm lead pitch e2 b b 16 15 8 9 e c 0.08 c ccc a a1 c a3 seating plane 1 l index area (d/2 x e/2) top view d c aaa 2 x c aaa 2 x e 1 17 24 25 32 d2 b c bbb m a 5 4 notes: 1. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. 2. falls within jedec, mo-220, variation vhhd-5. 3. all dimensions are in millimetres. 4. the terminal #1 identifier and terminal numbering convention shall conform to jedec 95-1 spp-002. 5. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. refer to application note wan_0118 for further information regarding pcb footprints and qfn package soldering. 7. this drawing is subject to change without notice. detail 1 a3 g t h w b exposed lead half etch tie bar dimensions (mm) symbols min nom max note a a1 a3 0.80 0.90 1.00 0.05 0.02 0 0.203 ref b d d2 e e2 e l 0.30 0.18 5.00 bsc 3.60 3.45 3.30 0.50 bsc 0.30 0.40 0.50 1 2 2 5.00 bsc 3.60 3.45 3.30 0.10 aaa bbb ccc ref: 0.15 0.10 jedec, mo-220, variation vhhd-5. tolerances of form and position 0.25 h 0.1 0.20 g t 0.103 w 0.15 detail 1 detail 2 detail 2 exposed ground paddle 6 exposed ground paddle bottom view side view 0.30 45 m m
wm8960 production data w pd, october 2011, rev 4.1 90 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specific ations in effect at the date of shipment. wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant informati on from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not nece ssarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfs on is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support sy stems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is per missible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other noti ces (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address: wolfson microelectronics plc 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com
production data wm8960 w pd, october 2011, rev 4.1 91 revision history date rev originator changes 23/09/11 4.1 jmacd order codes changed from wm8960gefl/v and wm8960gefl/rv to wm8960 c gefl/v and wm8960 c gefl/rv to reflect change to copper wire bonding. 23/09/11 4.1 jmacd package diagram changed to dm101.a.

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